ZHCSQ92B march   2022  – june 2023 AFE7903

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4说明（续）
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Transmitter Electrical Characteristics
    6. 6.6  RF ADC Electrical Characteristics
    7. 6.7  PLL/VCO/Clock Electrical Characteristics
    8. 6.8  Digital Electrical Characteristics
    9. 6.9  Power Supply Electrical Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Switching Characteristics
    12. 6.12 Typical Characteristics
      1. 6.12.1  RX Typical Characteristics 30 MHz and 400 MHz
      2. 6.12.2  RX Typical Characteristics at 800 MHz
      3. 6.12.3  RX Typical Characteristics 1.75 GHz to 1.9 GHz
      4. 6.12.4  RX Typical Characteristics 2.6 GHz
      5. 6.12.5  RX Typical Characteristics 3.5 GHz
      6. 6.12.6  RX Typical Characteristics 4.9 GHz
      7. 6.12.7  RX Typical Characteristics 6.8 GHz
      8. 6.12.8  TX Typical Characteristics at 30 MHz and 600 MHz
      9. 6.12.9  TX Typical Characteristics at 800 MHz
      10. 6.12.10 TX Typical Characteristics at 1.8 GHz
      11. 6.12.11 TX Typical Characteristics at 2.6 GHz
      12. 6.12.12 TX Typical Characteristics at 3.5 GHz
      13. 6.12.13 TX Typical Characteristics at 4.9 GHz
      14. 6.12.14 TX Typical Characteristics at 7.1 GHz
      15. 6.12.15 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 Trademarks
    4. 7.4 静电放电警告
    5. 7.5 术语表
  9. 9Mechanical, Packaging, and Orderable Information

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6.10 Timing Requirements

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
MIN NOM MAX UNIT
Timing: SYSREF+/-
ts(SYSREF) Setup Time, SYSREF+/- Valid to Rising Edge of CLK+/- 50 ps
th(SYSREF) Hold Time, SYSREF+/- Valid after Rising Edge of CLK+/- 50 ps
Timing: Serial ports
ts(SDEN) Setup Time, SDEN to Rising Edge of SCLK 15 ns
th(SDEN) Hold Time, SDEN after last Rising Edge of SCLK (1) 5 + tSCLK ns
ts(SDIO) Setup Time, SDIO valid to Rising Edge of SCLK 15 ns
th(SDIO) Hold Time, SDIO valid after Rising Edge of SCLK 5 ns
t(SCLK)_W Minimum SCLK period: registers write 25 ns
t(SCLK)_R Minimum SCLK period: registers read 50 ns
td(data_out) Minimum Data Output delay after Falling Edge of SCLK 0 ns
Maximum Data Output delay after Falling Edge of SCLK 15 ns
tRESET Minimum RESETZ Pulse Width 1 ms
(1) SDEN need to be held one more extra clock cycle with the last SCLK edge