1 Features

AFE5932 supports:
- 32-channels attenuator, PGA+LPF, 12-bit ADC, digital features with a decimation block
Input Attenuator (ATTEN) with DTGC
- 24dB to 0dB attenuation range with 0.125dB step. Using in-built DTGC engine attenuation can be changed in real time.
Post-gain Amplifier (PGA) and low-pass filter LPF
- Programmable gain of 12, 15 & 18 dB
- Maximum output swing support 1.6 Vpp
- LPF supported corners: First order filter with corner 10, 15 & 20 MHz
Analog to digital convertor
- Maximum input swing support: 1.6 Vpp
- Resolution: 12bit
- Maximum ADC clock frequency (f_{ADC_CLK}): 50MHz
- Full scale SNR: 62 dBFS
Decimation: Optional decimation block after ADC to decimate data by 2 or 4.
Compression block to combine data in fewer LVDS lanes as per the decimation factor
Total Power: 17 mW/ch at ADC Clock of 50MHz
Low speed CMOS serial programming interface to program front end and ADC upto 40MHz speed
Supply: 1.8V and 1.15V
Small package: FC-BGA-100 (10mm × 10mm) with 0.8mm pitch