ZHCSMK3B November   2020  – November 2021 ADS131B04-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Internal Test Signals
      6. 8.3.6  Clocking
        1. 8.3.6.1 External Clock Using CLKIN Pin
        2. 8.3.6.2 Internal Oscillator
      7. 8.3.7  ΔΣ Modulator
      8. 8.3.8  Digital Filter
        1. 8.3.8.1 Digital Filter Implementation
          1. 8.3.8.1.1 Fast-Settling Filter
          2. 8.3.8.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.8.2 Digital Filter Characteristic
      9. 8.3.9  Calibration Registers
      10. 8.3.10 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Synchronization
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  SPI Communication Frames
        7. 8.5.1.7  SPI Communication Words
        8. 8.5.1.8  Short SPI Frames
        9. 8.5.1.9  Communication Cyclic Redundancy Check (CRC)
        10. 8.5.1.10 SPI Timeout
      2. 8.5.2 ADC Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0110 0110)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Troubleshooting
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Minimum Interface Connections
      5. 9.1.5 Multiple Device Configuration
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
        3. 9.2.2.3 Shunt Temperature Measurement
        4. 9.2.2.4 Auxiliary Analog Supply Voltage Measurement
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Capacitor Requirement
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.4.2 Fast Start-Up Behavior

The ADS131B04-Q1 begins generating conversion data shortly after start-up as soon as a valid MCLK signal is provided to the ΔΣ modulators. Fast start-up is accomplished via two mechanisms. First, the device internal power-supply circuitry is designed specifically to enable fast start-up. Second, the digital decimation filter dynamically switches from a fast-settling filter to a sinc3 filter when the sinc3 filter has settled.

After the supplies are ramped to 90% of their final values, the device requires tPOR for the internal circuitry to settle. The end of tPOR is indicated by a transition of DRDY from low to high. The transition of DRDY from low to high also indicates the SPI interface is ready to accept commands.

The ΔΣ modulators of the ADS131B04-Q1 require CLKIN to toggle after tPOR to begin working, or alternatively, activate the internal oscillator by setting the CLK_SEL bit in the CLOCK register. The modulators begin sampling the input signal after an initial wait time delay of (256 + 44) × tMOD when MCLK begins toggling. Therefore, when using an external clock, provide a valid clock signal on CLKIN as soon as possible after the supply ramp to achieve the fastest possible start-up time.

The data generated by the ΔΣ modulators are fed to the digital filter blocks. The data are provided to both the fast-settling filter and the sinc3 filter paths. The fast-settling filter requires only one data rate period to provide settled data. Meanwhile, the sinc3 filter requires three data rate periods to settle. The fast-settling filter generates the output data for the two interim ADC output samples indicated by DRDY transitioning from high to low while the sinc3 filter is settling. The device disables the fast-settling filter and provides conversion data from the sinc3 filter path for the third and following samples. Figure 8-11 shows the behavior of the fast-start-up feature when using an external clock that is provided to the device right after the supplies have ramped. Table 8-7 shows the values for the various start-up and settling times relevant to the device start-up.

GUID-20201021-CA0I-CSHD-NFSN-PQFZVT5D3H7N-low.gif Figure 8-11 Fast Start-Up Behavior and Settling Times
Table 8-7 Fast Start-Up Settling Times for Default OSR = 1024
PARAMETER VALUE (DETAILS)
(tMOD) 		VALUE
(tMOD)		 VALUE AT
fMCLK = 8.192 MHz (ms)
tDATA = 1/fDATA 1024 1024 0.250
tSETTLE1 256 + 44 + 1024 1324 0.323
tSETTLE3 256 + 44 + 3 × 1024 3372 0.823

The fast-settling filter provides conversion data that are significantly noisier than the data that comes from the sinc3 filter path, but allows the device to provide settled conversion data during the longer settling time of the more accurate sinc3 digital filter. If the level of precision provided by the fast-settling filter is insufficient even for the first samples immediately following start-up, ignore the first two instances of DRDY toggling from high to low and begin collecting data on the third instance.

The start-up process following a RESET command or a pin reset using the SYNC/RESET pin is similar to what occurs after power up. However there is no tPOR in the case of a command or pin reset because the supplies are already ramped. After reset, the device waits for the initial wait time delay of (256 + 44) × tMOD before providing modulator samples to the two digital filters. The fast-settling filter is enabled for the first two output samples. Remember to enable the internal oscillator every time again after a reset in case the internal oscillator is to be used, because the device defaults to using an external clock.