Table 9. PGA Full-Scale Range

9.3.2.1 PGA Input-Voltage Requirements

As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded. The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA output. The specified minimum and maximum absolute input voltages (V_AINP and V_AINN) depend on the PGA gain, the maximum differential input voltage (V_INMAX), and the tolerance of the analog power-supply voltages (AVDD and AVSS). Use the maximum voltage expected in the application for V_INMAX. The absolute positive and negative input voltages must be within the specified range, as shown in Equation 5:

As mentioned in the previous section, PGA gain settings of 64 and 128 are scaled in the digital domain and are not implemented with the amplifier. When using the PGA in gains of 64 and 128, set the gain in Equation 5 to 32 to calculate the absolute input voltage range.

The relationship between the PGA input to the PGA output is shown graphically in Figure 51. The PGA output voltages (V_OUTP, V_OUTN) depend on the PGA gain and the input voltage magnitudes. For linear operation, the PGA output voltages must not exceed AVDD – 0.15 V or AVSS + 0.15 V. Note that the diagram depicts a positive differential input voltage that results in a positive differential output voltage.

Figure 51. PGA Input/Output Range

Download the ADS1x4S0x design calculator from www.ti.com. This calculator can be used to determine the input voltage range of the PGA.

9.3.2.2 PGA Rail Flags

The PGA rail flags (FL_P_RAILP, FL_P_RAILN, FL_N_RAILP, and FL_N_RAILN) in the status register (01h) indicate if the positive or negative output of the PGA is closer to the analog supply rails than 150 mV. Enable the PGA output rail detection circuit using the FL_RAIL_EN bit in the excitation current register 1 (06h). A flag going high indicates that the PGA is operating outside the linear operating or absolute input voltage range. PGA rail flags are discussed in more detail in the PGA Output Voltage Rail Monitors section.

9.3.2.3 Bypassing the PGA

At a gain of 1, the device can be configured to disable and bypass the low-noise PGA. Disabling the PGA lowers the overall power consumption and also removes the restrictions of Equation 5 for the input voltage range. If the PGA is bypassed, the ADC absolute input voltage range extends beyond the AVDD and AVSS power supplies, allowing input voltages at or below ground. The absolute input voltage range when the PGA is bypassed is shown in Equation 6:

In order to measure single-ended signals that are referenced to AVSS (AIN_P = V_IN, AIN_N = AVSS), the PGA must be bypassed. The PGA is bypassed and powered down by setting the PGA_EN[1:0] bits to 00 in the gain setting register (03h).

For signal sources with high output impedance, external buffering may still be necessary. Note that active buffers introduce noise and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.

9.3.3.1 Internal Reference

The ADC integrates a precision, low-drift, 2.5-V reference. The internal reference is enabled by setting REFCON[1:0] to 10 (reference is always on) or 01 (reference is on, but powers down in power-down mode) in the reference control register (05h). By default, the internal voltage reference is powered down. To select the internal reference for use with the ADC, set the REFSEL[1:0] bits to 10. The REFOUT pin provides a buffered reference output voltage when the internal reference voltage is enabled. The negative reference output is the REFCOM pin, as shown in Figure 52. Connect a capacitor in the range of 1 μF to 47 μF between REFOUT and REFCOM. Larger capacitor values help filter more noise at the expense of a longer reference start-up time.

The capacitor is not required if the internal reference is not used. However, the internal reference must be powered on if using the IDACs.

The internal reference requires a start-up time that must be accounted for before starting a conversion, as shown in Table 10.

9.3.3.2 External Reference

The ADS124S0x provides two external reference inputs selectable through the reference multiplexer. The reference inputs are differential with independent positive and negative inputs. REFP0 and REFN0 or REFP1 and REFN1 can be selected as the ADC reference. REFP1 and REFN1 are shared inputs with analog pins AIN6 and AIN7 in the ADS124S08.

Without buffering, the reference input impedance is approximately 250 kΩ. The reference input current can lead to possible errors from either high reference source impedance or through reference input filtering. To reduce the input current, use either internal or external reference buffers. In most applications external reference buffering is not necessary.

Connect a 100-nF bypass capacitor across the external reference input pins. Follow the specified absolute and differential reference voltage requirements.

9.3.3.3 Reference Buffers

The device has two individually selectable reference input buffers to lower the reference input current. Use the REFP_BUF and REFN_BUF bits in the reference control register (05h) to enable or disable the positive and negative reference buffers respectively. Note that these bits are active low. Writing a 1 to REFP_BUF or REFN_BUF disables the reference buffers.

The reference buffers are recommended to be disabled when the internal reference is selected for measurements. When the external reference input is at the supply voltage (REFPx at AVDD or REFNx at AVSS), the reference buffer is recomended to be disabled.

Table 11. ADC Data Rates and Digital Filter Oversampling Ratios

9.3.6.1 Low-Latency Filter

The low-latency filter is selected when the FILTER bit is set to 0 in the data rate register (04h). The filter is a finite impulse response (FIR) filter that provides settled data, given that the analog input signal has settled to the final value before the conversion is started. The low-latency filter is especially useful when multiple channels must be scanned in minimal time.

9.3.6.1.1 Low-Latency Filter Frequency Response

The low-latency filter provides many data rate options for rejecting 50-Hz and 60-Hz line cycle noise. At data rates of 2.5 SPS, 5 SPS, 10 SPS, and 20 SPS, the filter rejects both 50-Hz and 60-Hz line frequencies. At data rates of 16.6 SPS and 50 SPS, the filter has a notch at 50 Hz. At a 60-SPS data rate, the filter has a notch at 60 Hz.

For detailed frequency response plots showing line cycle noise rejection, download the ADS1x4S0x design calculator from www.ti.com.

Figure 54 to Figure 68 show the frequency response of the low-latency filter for different data rates. Table 12 gives the bandwidth of the low-latency filter for each data rate.

fCLK = 4.096 MHz, low-latency filter

Figure 54. Low-Latency Filter Frequency Response,
Data Rate = 2.5 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 56. Low-Latency Filter Frequency Response,
Data Rate = 10 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 58. Low-Latency Filter Frequency Response,
Data Rate = 20 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 60. Low-Latency Filter Frequency Response,
Data Rate = 50 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 62. Low-Latency Filter Frequency Response,
Data Rate = 100 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 64. Low-Latency Filter Frequency Response,
Data Rate = 400 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 66. Low-Latency Filter Frequency Response,
Data Rate = 1 kSPS

fCLK = 4.096 MHz, low-latency filter

Figure 68. Low-Latency Filter Frequency Response,
Data Rate = 4 kSPS

fCLK = 4.096 MHz, low-latency filter

Figure 55. Low-Latency Filter Frequency Response,
Data Rate = 5 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 57. Low-Latency Filter Frequency Response,
Data Rate = 16.6 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 59. Low-Latency Filter Frequency Response,
Data Rate = 20 SPS, Zoomed to 50 Hz and 60 Hz

fCLK = 4.096 MHz, low-latency filter

Figure 61. Low-Latency Filter Frequency Response,
Data Rate = 60 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 63. Low-Latency Filter Frequency Response,
Data Rate = 200 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 65. Low-Latency Filter Frequency Response,
Data Rate = 800 SPS

fCLK = 4.096 MHz, low-latency filter

Figure 67. Low-Latency Filter Frequency Response,
Data Rate = 2 kSPS

Table 12. Low-Latency Filter Bandwidth

NOMINAL DATA RATE (SPS)(1)	–3-dB BANDWIDTH (Hz)(1)
2.5	1.1
5	2.2
10	4.7
16.6	7.4
20	13.2
50	22.1
60	26.6
100	44.4
200	89.9
400	190
800	574
1000	718
2000	718
4000	718

(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with f_CLK.

The low-latency filter notches and output data rate scale proportionally with the clock frequency. For example, a notch that appears at 20 Hz when using a 4.096-MHz clock appears at 10 Hz if a 2.048-MHz clock is used. Note that the internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate, conversion time, and filter notches consequently vary by the same percentage. Consider using an external precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.

9.3.6.2 Sinc³ Filter

The sinc³ digital filter is selected when the FILTER bit is set to 0 in the data rate register (04h). Compared to the low-latency filter, the sinc³ filter has improved noise performance but has a three-cycle latency in the data output.

9.3.6.2.1 Sinc³ Filter Frequency Response

The low-pass nature of the sinc³ filter establishes the overall frequency response. The frequency response is given by Equation 8:

Equation 8.

where

• f = signal frequency
• f_CLK = ADC clock frequency
• OSR = oversampling ratio

The sinc³ filter offers simultaneous 50-Hz and 60-Hz line cycle rejection at data rates of 2.5 SPS, 5 SPS, and 10 SPS. The sinc³ filter offers only 50-Hz rejection at data rates of 16.6 SPS and 50 SPS, and only 60-Hz rejection at data rates of 20 SPS and 60 SPS. The sinc³ digital filter response scales with the data rate and has notches at multiples of the data rate. Figure 69 shows the sinc³ digital filter frequency response normalized to the data rate. As an example, Figure 70 shows the frequency response when the data rate is set to 10 SPS, and Figure 71 illustrates a close-up of the filter rejection of 50-Hz and 60-Hz line frequencies. For more detailed frequency response plots, download the ADS1x4S0x design calculator from www.ti.com.

Table 14 gives the bandwidth of the sinc³ filter for each data rate.

Frequency normalized to data rate, sinc3 filter

Figure 69. Sinc³ Filter Frequency Response,
Normalized to Data Rate

fCLK = 4.096 MHz, sinc3 filter

Figure 71. Sinc³ Filter Frequency Response,
Data Rate = 10 SPS, Zoomed to 50 Hz and 60 Hz

fCLK = 4.096 MHz, sinc3 filter

Figure 70. Sinc³ Filter Frequency Response,
Data Rate = 10 SPS

Table 14. Sinc³ Filter –3-dB Bandwidth

NOMINAL DATA RATE (SPS)(1)	–3-dB BANDWIDTH (Hz)(1)
2.5	0.65
5	1.3
10	2.6
16.6	4.4
20	5.2
50	13.1
60	15.7
100	26.2
200	52.3
400	105
800	209
1000	262
2000	523
4000	1046

(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with f_CLK.

As mentioned in the previous section, filter notches and output data rate scale proportionally with the clock frequency and the internal oscillator can change frequency with temperature.

9.3.6.3 Note on Conversion Time

Each data period consists of time required for the modulator to sample the analog inputs. However, there is additional time required before the samples become an ADC conversion result. First, there is a programmable conversion delay (described in the Programmable Conversion Delay section) that is added before the conversion starts. This delay allows for additional settling time for input filtering on the analog inputs and for the antialiasing filter after the PGA. The default programmable conversion delay is 14 · t_MOD. Also, overhead time is needed to convert the modulator samples into an ADC conversion result. This overhead time includes any necessary offset or gain compensation after the digital filter accumulates a data result.

The first conversion when the device is in continuous conversion mode (just as in single-shot conversion mode) includes the programmable conversion delay, the modulator sampling time, and the overhead time. The second and subsequent conversions are the normal data period (period as given by the inverse of the data rate).

Figure 72 shows the time sequence for the ADC in both continuous conversion and single-shot conversion modes. The sequence is the same regardless of the filter setting. However, when the low-latency filter settles for each data, the sinc³ filter does not settle until the third data.

1. Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.

2. In sinc³ filter mode, the first two data outputs are suppressed to allow for the measurement data to settle.

3. In sinc³ filter mode, there is no overhead time for the first two data, which are not available to be read.

Figure 72. Single-Shot Conversion Mode and Continuous Conversion Mode Sequences

9.3.6.4 50-Hz and 60-Hz Line Cycle Rejection

If the ADC connection leads are in close proximity to industrial motors and conductors, coupling of 50-Hz and
60-Hz power line frequencies can occur. The coupled noise interferes with the signal voltage, and can lead to inaccurate or unstable conversions. The digital filter provides enhanced rejection of power-line-coupled noise for data rates of 60 SPS and less. Program the filter to tradeoff data rate and conversion latency versus the desired level of line cycle rejection. Table 16 and Table 17 summarize the ADC 50-Hz and 60-Hz line-cycle rejection based on ±1-Hz and ±2-Hz tolerance of power-line to ADC clock frequency. The best possible power-line rejection is provided by using an accurate ADC clock.

9.3.6.5 Global Chop Mode

The device uses a very low-drift PGA and modulator in order to provide very low input voltage offset drift. However, a small amount of offset voltage drift sometimes remains in normal measurement. The ADC incorporates a global chop option to reduce the offset voltage and offset voltage drift to very low levels. When the global chop is enabled, the ADC performs two internal conversions to cancel the input offset voltage. The first conversion is taken with normal input polarity. The ADC reverses the internal input polarity for a second conversion. The average of the two conversions yields the final corrected result, removing the offset voltage. The global chop mode is enabled using the G_CHOP bit in the data rate register (04h). Figure 73 shows a block diagram of the global chop implementation. The combined PGA and ADC internal offset voltage is modeled as V_OFS.

Figure 73. ADC Global Chop Block Diagram

The first conversion result is available after the ADC takes two separate conversions with settled data. When using the low-latency filter, data settles in a single conversion. When the global chop mode is enabled, the first conversion result appears after a time period of approximately two conversions. When using the sinc³ filter, data settles in three conversions. If the global chop mode is enabled, the first conversion result appears after a time period of approximately six conversions.

In continuous conversion mode with the global chop mode enabled, subsequent conversions complete in half the time as the first conversion completed. Data for alternating inputs are pipelined so that averaging appears on each ADC data cycle. Conversion times using the global chop mode are given in Table 18 and Table 19.

In global chop mode, sequences are similar to taking consecutive single-shot conversions and swapping the input on each conversion. Output data are averaged using the last two data read operations by the ADC with the inputs swapped. Figure 74 shows the time sequence for the ADC using global chop mode.

1. Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.

2. When the first data are collected, the inputs are swapped.

3. Measurements are averaged after the inputs are swapped for each conversion.

Figure 74. Global Chop Enabled Conversion Mode Sequences

Because the digital filter must settle after reversing the inputs, the global chop mode data rate is less than the nominal data rate, depending on the digital filter and programmed settling delay. However, if the data rate in use has 50-Hz and 60-Hz frequency response notches, the null frequencies remain unchanged.

The global chop mode also reduces the ADC noise by a factor of √2 because two conversions are averaged. In some cases, the programmable conversion delay must be increased, DELAY[2:0] in the gain setting register (03h), to allow for settling of external components.

Table 20. VBIAS Settling Time

9.3.9.1 Internal Temperature Sensor

On-chip diodes provide temperature-sensing capability. Enable the internal temperature sensor by setting SYS_MON[2:0] = 010 in the system control register (09h). The temperature sensor outputs a voltage proportional to the device temperature as specified in the Electrical Characteristics table.

When measuring the internal temperature sensor, the analog inputs are disconnected from the ADC and the output voltage of the temperature sensor is routed to the ADC for measurement using the selected PGA gain, data rate, and voltage reference. If enabled, PGA gain must be limited to 4 for the temperature sensor measurement to remain within the allowed absolute input voltage range of the PGA. As a result of the low device junction-to-PCB thermal resistance (R_θJB), the internal device temperature closely tracks the printed circuit board (PCB) temperature.

9.3.9.2 Power Supply Monitors

The ADS124S0x provides a means for monitoring both the analog and digital power supply (AVDD and DVDD). The power-supply voltages are divided by a resistor network to reduce the voltages to within the ADC input range. The reduced power-supply voltage is routed to the ADC input multiplexer. The analog (V_ANLMON) and digital (V_DIGMON) power-supply readings are scaled by Equation 9 and Equation 10, respectively:

Enable the supply voltage monitors using the SYS_MON[2:0] bits in the system control register (09h). Setting SYS_MON[2:0] to 011 measures V_ANLMON, and setting SYS_MON[2:0] to 100 measures V_DIGMON.

When the supply voltage monitor is enabled, the analog inputs are disconnected from the ADC and the PGA gain is set to 1, regardless of the GAIN[2:0] bit values in the gain setting register (03h). Supply voltage monitor measurements can be done with either the PGA enabled or PGA disabled via the PGA_EN[1:0] register. To obtain valid power supply monitor readings, the reference voltage must be larger than the power-supply measurements shown in Equation 9 and Equation 10.

9.3.9.3 Burn-Out Current Sources

To help detect a possible sensor malfunction, the ADS124S0x provides selectable current sources to function as burn-out current sources (BOCS) using the SYS_MON[2:0] bits in the system control register (09h). Current sources are set to values of 0.2 µA, 1 µA, and 10 µA with SYS_MON[2:0] settings of 101, 110, and 111, respectively.

When enabled, one BOCS sources current to the selected positive analog input (AIN_P) and the other BOCS sinks current from the selected negative analog input (AIN_N). With an open-circuit in a burned out sensor, these BOCSs pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading can also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading can indicate a shorted sensor. Distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. The voltage drop across the external filter resistance and the residual resistance of the multiplexer can cause the output to read a value higher than zero.

The ADC readings of a functional sensor can be corrupted when the burn-out current sources are enabled. The burn-out current sources are recommended to be disabled when performing the precision measurement, and only enabling them to test for sensor fault conditions. If the global chop mode is enabled, disable this mode before making a measurement with the burn-out current sources.

9.3.10.1 POR Flag

After the power supplies are turned on, the ADC remains in reset until DVDD, IOVDD, and the analog power supply (AVDD – AVSS) voltage exceed the respective power-on reset (POR) voltage thresholds. If a POR event has occurred, the FL_POR flag (bit 7 of the STATUS byte) is set. This flag indicates that a POR event has occurred and has not been cleared. This flag is cleared with a user register write to set the bit to 0. The power-on reset is described further in the Power-On Reset section.

9.3.10.2 RDY Flag

The RDY flag indicates that the device has started up and is ready to receive a configuration change. During a reset or POR event, the device is resetting the register map and may not be available. The RDY flag is shown with bit 6 of the STATUS byte.

9.3.10.3 PGA Output Voltage Rail Monitors

The PGA contains an integrated output-voltage monitor. If the level of the PGA output voltage exceeds
AVDD – 0.15 V or drops below AVSS + 0.15 V, a flag is set to indicate that the output has gone beyond the output range of the PGA. Each PGA output V_OUTN and V_OUTP can trigger an overvoltage or undervoltage flag, giving a total of four flags. The PGA output voltage rail monitors are enabled with the FL_REF_EN bit of excitation current register 1. The PGA output voltage rail monitor block diagram is shown in Figure 77. If the PGA is bypassed, then the rail monitor is still operational and is sensing the connection at the input of the ADC.

The PGA output voltage rail monitors are:

• FL_P_RAILP (bit 5 of the STATUS byte): V_OUTP has exceeded AVDD – 0.15 V
• FL_P_RAILN (bit 4 of the STATUS byte): V_OUTP dropped below AVSS + 0.15 V
• FL_N_RAILP (bit 3 of the STATUS byte): V_OUTN has exceeded AVDD – 0.15 V
• FL_N_RAILN (bit 2 of the STATUS byte): V_OUTN dropped below AVSS + 0.15 V

Figure 77. PGA Output Voltage Rail Monitors

Figure 78 shows an example of a PGA output voltage rail monitor overrange event and the respective behavior of the flags. A fault is latched during a conversion cycle. The flags are updated (set or cleared) only at the end of a conversion cycle.

Figure 78. PGA Output Voltage Rail Monitor Timing

9.3.10.4 Reference Monitor

The user can select to continuously monitor the ADC reference inputs for a shorted or missing reference voltage. The reference detection circuit offers two thresholds, the first threshold is 300 mV and the second threshold is
1/3 · (AVDD – AVSS). The reference detection circuit measures the differential reference voltage and sets a flag latched after each conversion in the STATUS byte if the voltage is below the threshold. A reference voltage less than 300 mV can indicate a potential short on the reference inputs or, in case of a ratiometric RTD measurement, a broken wire between the RTD and the reference resistor. A reference voltage between 300 mV and 1/3 · (AVDD – AVSS) can indicate a broken sensor excitation wire in a 3-wire RTD setup.

Additionally, a resistor of 10 MΩ can be connected between the selected REFPx and REFNx inputs. The resistor can be used to detect a floating reference input. With a floating input, the resistor pulls both reference inputs to the same potential so that the reference detection circuit can detect this condition. The pull-together reference resistor is not recommended to be continuously connected to active reference inputs. This resistor lowers the input impedance of the reference inputs and can contribute gain error to the measurement.

The reference detection circuits must be enabled with the FL_REF_EN[1:0] bits of the reference control register (05h). The FL_REF_L0 flag (bit 0 of the STATUS byte) indicates if the reference voltage is lower than 0.3 V. The FL_REF_L1 flag (bit 1 of the STATUS byte) indicates if the reference voltage is lower than
1/3 · (AVDD – AVSS). A diagram of the reference detection circuit is shown in Figure 79. A reference monitor fault is latched at each conversion cycle and the flags in the status register are updated at the falling edge of DRDY.

Figure 79. Reference Monitor Block Diagram

9.3.14.1 Offset Calibration

The offset calibration word is 24 bits, consisting of three 8-bit registers, as shown in the three registers starting with offset calibration register 1. The offset value is twos complement format with a maximum positive value equal to 7FFFFFh, and a maximum negative value equal to 800000h. This value is subtracted from each output reading as an offset correction. A register value equal to 000000h has no offset correction. If global chop mode is enabled, the offset calibration register is disabled. Table 21 shows example settings of the offset register.

The user can select how many samples (1, 4, 8, or 16) to average for self or system offset calibration using the CAL_SAMP[1:0] bits in the system control register (09h). Fewer readings shorten the calibration time but also provide less accuracy. Averaging more readings takes longer but yields a more accurate calibration result by reducing the noise level.

Two commands can be used to perform offset calibration. SFOCAL is a self offset calibration that internally sets the input to mid-scale using the SYS_MON[2:0] = 001 setting and takes a measurement of the offset. SYOCAL is a system offset calibration where the user must input a null voltage to calibrate the system offset. After either command is issued, the OFC register is updated.

After an offset calibration is performed, the device starts a new conversion and DRDY falls to indicate a new conversion has completed.

9.3.14.2 Gain Calibration

The full-scale (gain) calibration word is 24 bits consisting of three 8-bit registers, as shown in the three registers starting with gain calibration register 1. The gain calibration value is straight binary, normalized to a unity-gain correction factor at a register value equal to 400000h. Table 22 shows register values for selected gain factors. Do not exceed the PGA input range limits during gain calibration.

All gains of the ADS124S0x are factory trimmed to meet the gain error specified in the Electrical Characteristics table at T_A = 25°C. When the gain drift of the devices over temperature is very low, there is typically no need for self gain calibration.

The SYGCAL command initiates a system gain calibration, where the user sets the input to full-scale to remove gain error. After the SYGCAL is issued, the FSC register is updated. As with the offset calibration, the CAL_SAMP[1:0] bits determine the number of samples used for a gain calibration.

As with an offset calibration, the device starts a new conversion after a gain calibration and DRDY falls to indicate a new conversion has completed.

9.4.1.1 Power-On Reset

The ADS124S0x incorporates a power-on reset circuit that holds the device in reset until all supplies reach approximately 1.65 V. The power-on reset also ensures that the device starts operating in a known state in case a brown-out event occurs, when the supplies have dipped below the minimum operating voltages. When the device completes a POR sequence, the FL_POR flag in the status register is set high to indicate that a POR has occurred.

Begin communications with the device 2.2 ms after the power supplies reach minimum operating voltages. The only exception is polling the status register for the RDY bit. If the user polls the RDY bit, then use an SCLK rate of half the maximum-specified SCLK rate to get a proper reading when the device is making internal configurations. This 2.2-ms POR time is required for the internal oscillator to start up and the device to properly set internal configurations. After the internal configurations are set, the device sets the RDY bit in the device status register (01h). When this bit is set to 0, user configurations can be programmed into the device. Figure 83 shows the power-on reset timing sequence for the device.

Figure 83. Power-On Reset Timing Sequence

9.4.1.2 RESET Pin

Reset the ADC by taking the RESET pin low for a minimum of 4 · t_CLK· cycles, and then returning the pin high. After the rising edge of the RESET pin, a delay time of t_d(RSSC) is required before sending the first serial interface command or starting a conversion. See the Timing Characteristics section for reset timing information.

9.4.1.3 Reset by Command

Reset the ADC by using the RESET command (06h or 07h). The command is decoded on the seventh SCLK falling edge. After sending the RESET command, a delay time of t_d(RSSC) is required before sending the first serial interface command or starting a conversion. See the Timing Characteristics section for reset timing information.

9.4.4.1 Continuous Conversion Mode

The device is configured for continuous conversion mode by setting the MODE bit to 0 in the data rate register (04h). A START command must be sent or the START/SYNC pin must be taken high for the device to start converting continuously. When controlling the device with commands, hold the START/SYNC pin low. Taking the START/SYNC pin low or sending the STOP command stops the device from converting after the currently ongoing conversion completes, indicated by the falling edge of DRDY. The device enters standby mode thereafter.

For information on the exact timing of single-shot conversion mode data, see Table 13 and Table 15.

9.4.4.2 Single-Shot Conversion Mode

The device is configured for single-shot conversion mode by setting the MODE bit to 1 in the data rate register (04h). A START command must be sent or the START/SYNC pin must be taken high for the device to start a single conversion. After the conversion completes, the device enters standby mode again. To start a new conversion, the START command must be sent again or the START/SYNC pin must be taken low and then high again.

When the device uses the sinc³ filter, ADC data requires three conversion cycles to settle. When the sinc³ filter is enabled, a single-shot conversion suppresses the first two ADC conversions and provides the third conversion as the output data so that the user receives settled data. Because three conversions are required for settled data, the conversion time in single-shot conversion mode is approximately three times the normal data period. When the device uses the low-latency filter, the ADC data settles in a single conversion. In single-shot conversion mode with the low-latency filter, the data period is closer to the normal data period.

For information on the exact timing of single-shot conversion mode data, see Table 13 and Table 15.

9.4.4.3 Programmable Conversion Delay

When a new conversion is started, the ADC provides a delay before the actual start of the conversion. This timed delay is provided to allow for the integrated analog anti-alias filter to settle. In some cases more delay is required to allow for external settling effects. The delay time can be configured to automatically delay the start of a conversion after a START command is sent, the START/SYNC pin is taken high, or a WREG command is sent to change any configuration register from address 03h to 07h is issued (as described in the WREG section). The programmable conversion delay is intended to accommodate the analog settling time on the inputs (for example, when changing a multiplexer channel). Use the DELAY[2:0] bits in the gain setting register (03h) to program a delay time ranging from 1 · t_MOD to 4096 · t_MOD (where t_MOD = 16 · t_CLK). The default programmable conversion delay setting is 14 · t_MOD.

9.5.1.1 Chip Select (CS)

The CS pin is an active low input that enables the ADC serial interface for communication and is useful when multiple devices share the same serial bus. CS must be low during the entire data transaction. When CS is high, the serial interface is reset, SCLK input activity is ignored (blocking input commands), and the DOUT/DRDY output enters a high-impedance state. ADC conversions are not affected by the state of CS. In situations where multiple devices are present on the bus, the dedicated DRDY pin can provide an uninterrupted monitor of the conversion status and is not affected by CS. If the serial bus is not shared with another peripheral, CS can be tied to DGND to permanently enable the ADC interface and DOUT/DRDY can be used to indicate conversion status. These changes reduce the serial interface from five I/Os to three I/Os.

9.5.1.2 Serial Clock (SCLK)

The serial interface clock is a noise-filtered, Schmidt-triggered input used to clock data into and out of the ADC. Input data to the ADC are latched on the falling SCLK edge and output data from the ADC are updated on the rising SCLK edge. Return SCLK low after the data sequence is complete. Even though the SCLK input has hysteresis, keep SCLK as clean as possible to prevent unintentional SCLK transitions. Avoid ringing and voltage overshoot on the SCLK input. Place a series termination resistor at the SCLK drive pin to help reduce ringing.

9.5.1.3 Serial Data Input (DIN)

The serial data input pin (DIN) is used with SCLK to send data (commands and register data) to the device. The device latches data on DIN on the SCLK falling edge. The device never drives the DIN pin. During data readback, when no command is intended, keep DIN low.

9.5.1.4 Serial Data Output and Data Ready (DOUT/DRDY)

The DOUT/DRDY pin is a dual-function output. The pin functions as the digital data output and the ADC data-ready indication.

First, this pin is used with SCLK to read conversion and register data from the device. Conversion or register data are shifted out on DOUT/DRDY on the SCLK rising edge. DOUT/DRDY goes to a high-impedance state when CS is high.

Second, the DOUT/DRDY pin indicates availability of new conversion data. DOUT/DRDY transitions low at the same time that the DRDY pin goes low to indicate new conversion data are available. Both signals can be used to detect if new data are ready. However, because DOUT/DRDY is disabled when CS is high, use the dedicated DRDY pin when monitoring conversions on multiple devices on the SPI bus.

9.5.1.5 Data Ready (DRDY)

The DRDY pin is an output that transitions low to indicate when conversion data are ready for retrieval. Initially, DRDY is high at power-on. When converting, the state of DRDY depends on whether the conversion data are retrieved or not. In continuous conversion mode after DRDY goes low, DRDY is driven high on the first SCLK rising edge. If data are not read, DRDY remains low and then pulses high 24 · t_CLK before the next DRDY falling edge. The data must be retrieved before the next DRDY update, otherwise the data are overwritten by new data and any previous data are lost. Figure 85 shows the DRDY operation without data retrieval. Figure 86 shows the DRDY operation with data retrieval after each conversion completes.

1. DRDY returns high with the rising edge of the first SCLK after a data ready indication.

Figure 85. DRDY Operation Without Data Retrieval

1. DRDY returns high with the rising edge of the first SCLK after a data ready indication.

Figure 86. DRDY Operation With Data Retrieval

9.5.1.6 Timeout

The ADS124S0x offers a serial interface timeout feature that is used to recover communication when a serial interface transmission is interrupted. This feature is especially useful in applications where CS is permanently tied low and is not used to frame a communication sequence. The SPI interface resets when no valid 8 bits are received within 2¹⁵ · t_CLK. The timeout feature is enabled by setting the TIMEOUT bit to 1 in the system control register (09h).

Table 23. Ideal Output Code vs Input Signal

Table 24. Command Definitions

9.5.3.1 NOP

NOP is a no-operation command. The NOP command is used to clock out data without clocking in a command.

9.5.3.2 WAKEUP

Issue the WAKEUP command to exit power-down mode and to place the device into standby mode.

When running off the external clock, the external clock must be running before sending the WAKEUP command, otherwise the command is not decoded.

9.5.3.3 POWERDOWN

Sending the POWERDOWN command aborts a currently ongoing conversion and puts the device into power-down mode. The device goes into power-down mode 2 · t_CLK after the seventh SCLK falling edge of the command.

For lowest power consumption on DVDD and IOVDD, stop the external clock when in power-down mode. The device does not gate the external clock. When running off the external clock, provide at a minimum two additional t_CLKs after the POWERDOWN command is issued, otherwise the device does not enter power-down mode. Because an external clock can be gated for lower power consumption, selecting the internal oscillator before sending the POWERDOWN command is recommended.

During power-down mode, the only commands that are available are RREG, RDATA, and WAKEUP.

9.5.3.4 RESET

The RESET command resets the digital filter and sets all configuration register values to default settings. A RESET command also puts the device into standby mode. When in standby mode, the device waits for a rising edge on the START/SYNC pin or a START command to resume conversions. After sending the RESET command, a delay time of t_d(RSSC) is required before sending the first serial interface command or starting a conversion. See the Timing Characteristics section for reset timing information.

Note that if the device had been using an external clock, the reset sets the device to use the internal oscillator as a default configuration.

9.5.3.5 START

When the device is configured for continuous conversion mode, issue the START command for the device to start converting. Every time a conversion completes, the device automatically starts a new conversion until the STOP command is sent.

In single-shot conversion mode, the START command is used to start a single conversion. After the conversion completes, the device enters standby mode.

Tie the START/SYNC pin low when the device is controlled through the START and STOP commands. The START command is not decoded if the START/SYNC pin is high. If the device is already in conversion mode, the command has no effect.

9.5.3.6 STOP

The STOP command is used in continuous conversion mode to stop the device from converting. The current conversion is allowed to complete. After DRDY transitions low, the device enters standby mode. The command has no effect in single-shot conversion mode.

Hold the START/SYNC pin low when the device is controlled through START and STOP commands.

9.5.3.7 SYOCAL

The SYOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be externally shorted to a voltage within the input range, ideally near the mid-supply voltage of (AVDD + AVSS) / 2. The OFC registers are updated when the command completes. Calibration commands must be issued in conversion mode.

9.5.3.8 SYGCAL

The SYGCAL command initiates the system gain calibration. For a system gain calibration, the input must be externally set to full-scale. The FSC registers are updated after this operation. Calibration commands must be issued in conversion mode.

9.5.3.9 SFOCAL

The SFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply and performs the calibration. The OFC registers are updated after this operation. Calibration commands must be issued in conversion mode.

9.5.3.10 RDATA

The RDATA command is used to read conversion data from the device at any time without concern of data corruption when the DRDY or DOUT/DRDY signal cannot be monitored. The conversion result is read from a buffer so that a new data conversion does not corrupt the conversion read.

9.5.3.11 RREG

Use the RREG command to read the device register data. Read the register data one register at a time, or read a block of register data. The starting register address can be any register in the register map. The RREG command consists of two bytes. The first byte specifies the starting register address: 001r rrrr, where r rrrr is the starting register address. The second command byte is the number of registers to read (minus 1): 000n nnnn, where n nnnn is the number of registers to read minus 1.

After the read command is sent, the ADC responds with one or more register data bytes, most significant bit first. If the byte count exceeds the last register address, the ADC begins to output zero data. During the register read operation, any conversion data that becomes available is not loaded to the output shift register to avoid data contention. However, the conversion data can be retrieved later by the RDATA command. After the register read command has started, further commands are blocked until one of the following conditions are met:

• The read operation is completed
• The read operation is terminated by taking CS high
• The read operation is terminated by a serial interface timeout
• The ADC is reset by toggling the RESET pin

Figure 88 depicts a two-register read operation example. As shown, the commands required to read data from two registers starting at register REF (address = 05h) are: command byte 1 = 25h and command byte 2 = 01h. Keep DIN low after the two command bytes are sent.

1. CS can be set high or kept low between commands. If kept low, the command must be completed.

Figure 88. Read Register Sequence

9.5.3.12 WREG

Use the WREG command to write the device register data. The register data are written one register at a time or as a block of register data. The starting register address is any register in the register map.

The WREG command consists of two bytes. The first byte specifies the starting register address: 010r rrrr, where r rrrr is the starting register address The second command byte is the number of registers to write (minus 1): 000n nnnn, where n nnnn is the number of registers to write minus 1. The following byte (or bytes) is the register data, most significant bit first. If the byte count exceeds the last register address, the ADC ignores the data. After the register write command has started, further commands are blocked until one of the following conditions are met:

• The write operation is completed
• The write operation is terminated by taking CS high
• The write operation is terminated by a serial interface timeout
• The ADC is reset by toggling the RESET pin

Figure 89 depicts a two-register write operation example. As shown, the required commands to write data to two registers starting at register REF (address = 05h) are: command byte 1 = 45h and command byte 2 = 01h.

1. CS can be set high or kept low between commands. If kept low, the command must be completed.

Figure 89. Write Register Sequence

Writing new data to certain configuration registers resets the digital filter and starts a new conversion if a conversion is in progress. Writing to the following registers triggers a new conversion:

• Channel configuration register (02h)
• Gain setting register (03h)
• Data rate register (04h)
• Reference control register (05h), bits [5:0]
• Excitation current register 1 (06h), bits [3:0]
• Excitation current register 2 (07h)
• System control register (09h), bits [7:5]

When the device is configured with WREG, the first data ready indication occurs after the new conversion completes with the new configuration settings. The previous conversion data are cleared at restart; therefore read the previous data before the register write operation. A WREG to the previously mentioned registers only starts a new conversion if the register data are new (differs from the previous register data) and if a conversion is in progress. If the device is in standby mode, the device sets the configuration according to the WREG data, but does not start a conversion until the START/SYNC pin is taken high or a START command is issued.

9.5.4.1 Read Data Direct

In this method of data retrieval, ADC conversion data are shifted out directly from the output shift register. No command is necessary. Read data direct requires that no serial activity occur from the falling edge of DRDY to the readback, or the data are invalid. The serial interface is full duplex in the read data direct mode; meaning that commands are decoded during the data readback. If no command is intended, keep DIN low during readback. If an input command is sent during readback, the ADC executes the command, and data corruption can result. Synchronize the data readback to DRDY or to DOUT/DRDY to make sure the data are read before the next DRDY update, or the old data are overwritten with new data.

As shown in Figure 90, the ADC data field is 3, 4, or 5 bytes long. The data field consists of an optional STATUS byte, three bytes of conversion data, and an optional CRC byte. After all bytes are read, the data-byte sequence (including the STATUS byte and CRC byte, if selected) is repeated when continued SCLKs are sent. The byte sequence repeats starting with the first byte. In order to help verify error-free communication, read the same data multiple times in each conversion interval or use the optional CRC byte.

1. DRDY returns high on the first SCLK falling edge.

2. CS can be tied low. If CS is low, DOUT/DRDY asserts low at the same time as DRDY.

3. Complete data retrieval before new data are ready (28 · t_CLK before the next falling edge of DOUT/DRDY and DRDY).

4. The STATUS and CRC bytes are optional.

5. The byte sequence, including selected optional bytes, repeats by continuing SCLK.

Figure 90. Read Data Direct

9.5.4.2 Read Data by RDATA Command

When the RDATA command is sent, the data are retrieved from the ADC data-holding register. Read data at any time without the risk of data corruption because the command method does not require synchronizing to DRDY. Polling of DRDY to determine when ADC data are ready can still be used.

Figure 91 shows the read data by command sequence. The output data MSB begins on the first SCLK rising edge after the command. The output data field can be 3, 4, or 5 bytes long. The data field consists of an optional STATUS byte, three bytes of conversion data, and an optional CRC byte. An RDATA command must be sent for each read operation. The ADC does not respond to commands until the read operation is complete, or terminated by taking CS high.

After all bytes are read, the data-byte sequence (including the STATUS byte and CRC byte, if selected) is repeated by continuing SCLK.

1. CS can be tied low. If CS is low, DOUT/DRDY asserts low with DRDY.

2. DOUT/DRDY is driven low with DRDY. If a read operation occurs after the DRDY falling edge, then DOUT/DRDY can be high or low.

3. The STATUS and CRC bytes are optional.

Figure 91. Read Data by Command

9.5.4.3 Sending Commands When Reading Data

The device serial interface is capable of full-duplex operation when reading conversion data and not using the RDATA command. In full-duplex operation, commands are decoded at the same time that conversion data are read. Commands can be sent on any 8-bit data boundary during a data read operation. When a RREG or RDATA command is recognized, the current data read operation is aborted and the conversion data are corrupted, unless the command is sent when the last byte of the conversion result is retrieved. The device starts to output the requested data on DOUT/DRDY at the first SCLK rising edge after the command byte. To read data without interruption, keep DIN low when clocking out data.

A WREG command can be sent without corrupting an ongoing read operation. Sending a WREG command when reading data minimizes the time between reading the data and setting the device configuration for the next conversion. Figure 92 shows an example for sending a WREG command to write two configuration registers when reading conversion data by using read data direct mode. After the command is clocked in, the device resets the digital filter and starts converting with the new register settings as long as the device is in continuous conversion mode. The digital filter is reset and conversions are restarted after each data byte is received. In this example, the digital filter is reset when the first byte is received, decoding the input multiplexer and again when the PGA is set. The WREG command can be sent on any of the 8-bit boundaries. The example in Figure 92 has the STATUS and CRC bytes disabled.

1. CS can be tied low. If CS is low, DOUT/DRDY asserts low at the same time as DRDY.

2. The output data buffer is cyclical and the original data byte is re-issued when the fourth DIN byte is clocked in.

Figure 92. Issuing a WREG Command When Reading Back ADC Data

Table 25. Configuration Register Map

9.6.1.1 Device ID Register (address = 00h) [reset = xxh]

9.6.1.2 Device Status Register (address = 01h) [reset = 80h]

9.6.1.3 Input Multiplexer Register (address = 02h) [reset = 01h]

9.6.1.4 Gain Setting Register (address = 03h) [reset = 00h]

9.6.1.5 Data Rate Register (address = 04h) [reset = 14h]

9.6.1.6 Reference Control Register (address = 05h) [reset = 10h]

9.6.1.7 Excitation Current Register 1 (address = 06h) [reset = 00h]

9.6.1.8 Excitation Current Register 2 (address = 07h) [reset = FFh]

9.6.1.9 Sensor Biasing Register (address = 08h) [reset = 00h]

9.6.1.10 System Control Register (address = 09h) [reset = 10h]

9.6.1.11 Offset Calibration Register 1 (address = 0Ah) [reset = 00h]

9.6.1.12 Offset Calibration Register 2 (address = 0Bh) [reset = 00h]

9.6.1.13 Offset Calibration Register 3 (address = 0Ch) [reset = 00h]

9.6.1.14 Gain Calibration Register 1 (address = 0Dh) [reset = 00h]

9.6.1.15 Gain Calibration Register 2 (address = 0Eh) [reset = 00h]

9.6.1.16 Gain Calibration Register 3 (address = 0Fh) [reset = 40h]

9.6.1.17 GPIO Data Register (address = 10h) [reset = 00h]

9.6.1.18 GPIO Configuration Register (address = 11h) [reset = 00h]