ZHCSIU3 September 2018 ADS1235
PRODUCTION DATA.
The ADS1235 is a three differential-input, precision 24-bit, ΔΣ ADC with a low-noise PGA and programmable digital filter. The low-noise, low-drift architecture of the PGA makes the ADC suitable for precision measurement of low signal level sensors, such as strain-gauge bridges and resistive pressure transducers. The ADC provides optional chop and ac-bridge excitation modes to eliminate offset drift error.
Key features of the ADC are:
The analog inputs (AINx) connect to the input multiplexer (MUX). The ADC supports three differential or five single-ended input measurement configurations. A second voltage reference input and AC-bridge excitation drive outputs (GPIO) are multiplexed with the analog input pins.
The programmable gain amplifier (PGA) follows the input multiplexer. The gain is programmable to 1, 64 or 128. The PGA bypass option connects the analog inputs directly to the precharge buffered modulator, extending the input voltage range to the voltage of the power supplies. The PGA output connects to pins CAPP and CAPN. The ADC antialias filter is provided at the PGA output with an external capacitor. A monitor is used for detection of PGA overrange conditions.
The delta-sigma modulator measures the differential input voltage relative to the reference voltage to produce the 24-bit conversion result. The differential input range of the ADC is ±VREF / Gain.
The digital filter averages and decimates the modulator output data to yield the final, down-sampled conversion result. The sinc filter is programmable (sinc1 through sinc4) allowing optimization of conversion time, conversion noise and line-cycle rejection. The finite impulse response (FIR) filter mode provides single-cycle settled data with simultaneous rejection of 50-Hz and 60-Hz at data rates of 20 SPS or less.
Two reference voltage input pairs are provided. The primary reference input pair (REFP0/REFN0) is available as standalone input pins. A second reference input pair (REFP1/REFN1) is multiplexed with analog inputs AIN0 and AIN1. A monitor is used for detection of low or missing reference voltage.
The ADC provides four GPIO control lines. The GPIOs are used for input and output of general-purpose logic signals, as well as providing output drive signals for ac-excited bridges. The GPIOs and ac-bridge excitation drive outputs are multiplexed to the analog inputs.
The internal temperature sensor voltage is read by the ADC through the analog input multiplexer.
The SPI-compatible serial interface is used to read the conversion data and also to configure and control the ADC. Data communication errors are detected by CRC. The serial interface consists of four signals: CS, SCLK, DIN and DOUT/DRDY. The dual function DOUT/DRDY provides data output and also the data ready signal. The ADC serial interface can be implemented with as little as three pins by tying CS low.
The ADC clock is either internal or external. The ADC detects the mode of clock operation automatically. The clock frequency is 7.3728 MHz.
Data conversions are controlled by the START pin or by the START command. The ADC is programmable for continuous or one-shot conversions. The DRDY or DOUT/DRDY pin provides the conversion-data ready signal. When taken low, the RESET pin resets the ADC. The ADC is powered down by the PWDN pin or is powered down in software mode.
The ADC operates in either bipolar analog supply configuration (±2.5 V), or in single 5-V supply configuration. The digital power supply range is 2.7 V to 5 V. The BYPASS pin is the internal subregulator output used for the ADC digital core.