ZHCSD67C July   2014  – March 2016 ADC3241 , ADC3242 , ADC3243 , ADC3244

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADC3241, ADC3242
    6. 7.6  Electrical Characteristics: ADC3243, ADC3244
    7. 7.7  Electrical Characteristics: General
    8. 7.8  AC Performance: ADC3241
    9. 7.9  AC Performance: ADC3242
    10. 7.10 AC Performance: ADC3243
    11. 7.11 AC Performance: ADC3244
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3241
    16. 7.16 Typical Characteristics: ADC3242
    17. 7.17 Typical Characteristics: ADC3243
    18. 7.18 Typical Characteristics: ADC3244
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 14x Serialization
        2. 9.3.3.2 Two-Wire Interface: 7x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
        1. 9.4.3.1 Improving Wake-Up Time From Global Power-Down
      4. 9.4.4 Internal Dither Algorithm
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Description
        1. 9.6.2.1  Register 01h
        2. 9.6.2.2  Register 03h
        3. 9.6.2.3  Register 04h
        4. 9.6.2.4  Register 05h
        5. 9.6.2.5  Register 06h
        6. 9.6.2.6  Register 07h
        7. 9.6.2.7  Register 09h
        8. 9.6.2.8  Register 0Ah
        9. 9.6.2.9  Register 0Bh
        10. 9.6.2.10 Register 0Eh
        11. 9.6.2.11 Register 0Fh
        12. 9.6.2.12 Register 13h (address = 13h)
        13. 9.6.2.13 Register 15h
        14. 9.6.2.14 Register 25h
        15. 9.6.2.15 Register 27h
        16. 9.6.2.16 Register 41Dh
        17. 9.6.2.17 Register 422h
        18. 9.6.2.18 Register 434h
        19. 9.6.2.19 Register 439h
        20. 9.6.2.20 Register 51Dh
        21. 9.6.2.21 Register 522h
        22. 9.6.2.22 Register 534h
        23. 9.6.2.23 Register 539h
        24. 9.6.2.24 Register 608h
        25. 9.6.2.25 Register 70Ah
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Analog supply voltage range, AVDD –0.3 2.1 V
Digital supply voltage range, DVDD –0.3 2.1 V
Voltage applied to input pins INAP, INBP, INAM, INBM –0.3 min (1.9, AVDD + 0.3) V
CLKP, CLKM –0.3 AVDD + 0.3
SYSREFP, SYSREFM –0.3 AVDD + 0.3
SCLK, SEN, SDATA, RESET, PDN –0.3 3.9
Temperature Operating free-air, TA –40 85 ºC
Operating junction, TJ 125
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(2)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage range 1.7 1.8 1.9 V
DVDD Digital supply voltage range 1.7 1.8 1.9 V
ANALOG INPUT
VID Differential input voltage For input frequencies < 450 MHz 2 VPP
For input frequencies < 600 MHz 1
VIC Input common-mode voltage VCM ± 0.025 V
CLOCK INPUT
Input clock frequency Sampling clock frequency 10 125(1) MSPS
Input clock amplitude (differential) Sine wave, ac-coupled 0.2 1.5 VPP
LVPECL, ac-coupled 1.6
LVDS, ac-coupled 0.7
Input clock duty cycle 35% 50% 65%
Input clock common-mode voltage 0.95 V
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF
RLOAD Differential load resistance placed externally 100 Ω
(1) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.
(2) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.

7.4 Thermal Information

THERMAL METRIC(1) ADC324x UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 25.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.9 °C/W
RθJB Junction-to-board thermal resistance 3.0 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: ADC3241, ADC3242

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC3241 ADC3242 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 125 125 MSPS
1.8-V analog supply current 31 71 39 81 mA
1.8-V digital supply current 35 65 43 75 mA
Total power dissipation 118 205 147 245 mW
Global power-down dissipation 5 17 5 17 mW
Standby power-down dissipation 78 103 78 103 mW

7.6 Electrical Characteristics: ADC3243, ADC3244

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC3243 ADC3244 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 80 125 MSPS
1.8-V analog supply current 50 91 65 106 mA
1.8-V digital supply current 52 85 64 95 mA
Total power dissipation 183 285 233 325 mW
Global power-down dissipation 5 17 5 17 mW
Standby power-down dissipation 72 103 78 103 mW

7.7 Electrical Characteristics: General

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 14 Bits
ANALOG INPUT
Differential input full-scale 2.0 VPP
RIN Input resistance Differential at dc 6.6 kΩ
CIN Input capacitance Differential at dc 3.7 pF
VOC(VCM) VCM common-mode voltage output 0.95 V
VCM output current capability 10 mA
Input common-mode current Per analog input pin 1.5 µA/MSPS
Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 540 MHz
DC ACCURACY
EO Offset error –25 25 mV
αEO Temperature coefficient of offset error ±0.024 °C
EG(REF) Gain error as a result of internal reference inaccuracy alone –2 2 %FS
EG(CHAN) Gain error of channel alone –2 %FS
α(EGCHAN) Temperature coefficient of EG(CHAN) ±0.008 Δ%FS/°C
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk(1) fIN = 10 MHz 105 dB
fIN = 100 MHz 105
fIN = 200 MHz 105
fIN = 230 MHz 105
fIN = 300 MHz 105
(1) Crosstalk is measured with a –1-dBFS input signal on one channel and no input on the other channel.

7.8 AC Performance: ADC3241

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3241 (fS = 25 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 73.3 73.7 dBFS
fIN = 20 MHz 69.7 73.4 73.7
fIN = 70 MHz 72.8 73.2
fIN = 100 MHz 72.4 72.8
fIN = 170 MHz 71.3 71.6
fIN = 230 MHz 70.1 70.4
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.2 72.6 dBFS
fIN = 20 MHz 72.3 72.6
fIN = 70 MHz 71.8 72.2
fIN = 100 MHz 71.5 71.9
fIN = 170 MHz 70.5 70.8
fIN = 230 MHz 69.3 69.6
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –143.9 –144.3 dBFS/Hz
fIN = 20 MHz –144.0 –140.7 –144.3
fIN = 70 MHz –143.4 –143.8
fIN = 100 MHz –143.0 –143.4
fIN = 170 MHz –141.9 –142.2
fIN = 230 MHz –140.7 –141.0
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 73.3 73.5 dBFS
fIN = 20 MHz 69.1 73.1 73.5
fIN = 70 MHz 72.8 72.9
fIN = 100 MHz 72.2 72.4
fIN = 170 MHz 71.2 71.2
fIN = 230 MHz 69.7 69.7
ENOB(1) Effective number of bits fIN = 10 MHz 11.9 11.9 Bits
fIN = 20 MHz 11.2 11.8 11.9
fIN = 70 MHz 11.8 11.8
fIN = 100 MHz 11.7 11.7
fIN = 170 MHz 11.5 11.5
fIN = 230 MHz 11.3 11.3
SFDR Spurious-free dynamic range fIN = 10 MHz 95 87 dBc
fIN = 20 MHz 84 94 89
fIN = 70 MHz 92 86
fIN = 100 MHz 85 81
fIN = 170 MHz 86 83
fIN = 230 MHz 81 79
HD2 Second-order harmonic distortion fIN = 10 MHz 104 96 dBc
fIN = 20 MHz 84 100 95
fIN = 70 MHz 100 95
fIN = 100 MHz 95 93
fIN = 170 MHz 87 87
fIN = 230 MHz 81 81
HD3 Third-order harmonic distortion fIN = 10 MHz 95 88 dBc
fIN = 20 MHz 84 94 92
fIN = 70 MHz 92 86
fIN = 100 MHz 85 82
fIN = 170 MHz 87 83
fIN = 230 MHz 82 80
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 100 92 dBc
fIN = 20 MHz 87 101 92
fIN = 70 MHz 100 92
fIN = 100 MHz 98 92
fIN = 170 MHz 100 92
fIN = 230 MHz 96 92
THD Total harmonic distortion fIN = 10 MHz 94 85 dBc
fIN = 20 MHz 80.5 92 85
fIN = 70 MHz 91 84
fIN = 100 MHz 86 82
fIN = 170 MHz 84 81
fIN = 230 MHz 78 76
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –94 –93 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –92 –90
(1) Reported from a 1-MHz offset.

7.9 AC Performance: ADC3242

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3242 (fS = 50 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 73.3 73.7 dBFS
fIN = 20 MHz 70.5 73.3 73.8
fIN = 70 MHz 73 73.3
fIN = 100 MHz 72.6 73.1
fIN = 170 MHz 71.7 72.1
fIN = 230 MHz 70.9 71.2
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.5 72.9
fIN = 20 MHz 72.6 73.1
fIN = 70 MHz 72.3 72.6
fIN = 100 MHz 71.9 72.4
fIN = 170 MHz 71.1 71.5
fIN = 230 MHz 70.3 70.6
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –147.1 –147.5 dBFS/Hz
fIN = 20 MHz –147.1 –144.5 –147.6
fIN = 70 MHz –146.8 –147.1
fIN = 100 MHz –146.4 –146.9
fIN = 170 MHz –145.5 –145.9
fIN = 230 MHz –144.7 –145
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 73.2 73.6 dBFS
fIN = 20 MHz 69.6 73.4 73.6
fIN = 70 MHz 72.9 73.2
fIN = 100 MHz 72.5 72.9
fIN = 170 MHz 71.5 71.7
fIN = 230 MHz 70.5 70.6
ENOB(1) Effective number of bits fIN = 10 MHz 11.9 11.9 Bits
fIN = 20 MHz 11.3 11.9 11.9
fIN = 70 MHz 11.8 11.9
fIN = 100 MHz 11.7 11.8
fIN = 170 MHz 11.6 11.6
fIN = 230 MHz 11.4 11.4
SFDR Spurious-free dynamic range fIN = 10 MHz 89 95 dBc
fIN = 20 MHz 83 93 91
fIN = 70 MHz 94 93
fIN = 100 MHz 88 86
fIN = 170 MHz 85 82
fIN = 230 MHz 82 80
HD2 Second-order harmonic distortion fIN = 10 MHz 103 97 dBc
fIN = 20 MHz 83 99 95
fIN = 70 MHz 96 94
fIN = 100 MHz 94 92
fIN = 170 MHz 88 89
fIN = 230 MHz 82 83
HD3 Third-order harmonic distortion fIN = 10 MHz 89 97 dBc
fIN = 20 MHz 83 93 95
fIN = 70 MHz 94 93
fIN = 100 MHz 88 86
fIN = 170 MHz 85 82
fIN = 230 MHz 82 80
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 96 dBc
fIN = 20 MHz 87 101 93
fIN = 70 MHz 100 94
fIN = 100 MHz 99 94
fIN = 170 MHz 99 93
fIN = 230 MHz 97 93
THD Total harmonic distortion fIN = 10 MHz 88 90 dBc
fIN = 20 MHz 79 92 87
fIN = 70 MHz 92 88
fIN = 100 MHz 89 86
fIN = 170 MHz 83 81
fIN = 230 MHz 79 78
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –95 –95 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –92 –89
(1) Reported from a 1-MHz offset.

7.10 AC Performance: ADC3243

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3243 (fS = 80 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 73.1 73.5 dBFS
fIN = 70 MHz 70.7 72.9 73.3
fIN = 100 MHz 72.7 73
fIN = 170 MHz 72 72.4
fIN = 230 MHz 71.4 71.7
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.4 72.8
fIN = 70 MHz 72.3 72.6
fIN = 100 MHz 72.1 72.3
fIN = 170 MHz 71.4 71.7
fIN = 230 MHz 70.9 71.2
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –149.0 –149.4 dBFS/Hz
fIN = 70 MHz –148.8 –146.7 –149.2
fIN = 100 MHz –148.6 –148.9
fIN = 170 MHz –147.9 –148.3
fIN = 230 MHz –147.3 –147.6
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 73.1 73.4 dBFS
fIN = 70 MHz 69.6 72.9 73.2
fIN = 100 MHz 72.7 72.9
fIN = 170 MHz 71.9 72.2
fIN = 230 MHz 71.2 71.3
ENOB(1) Effective number of bits fIN = 10 MHz 11.8 11.9 Bits
fIN = 70 MHz 11.3 11.8 11.9
fIN = 100 MHz 11.8 11.8
fIN = 170 MHz 11.6 11.7
fIN = 230 MHz 11.5 11.6
SFDR Spurious-free dynamic range fIN = 10 MHz 89 94 dBc
fIN = 70 MHz 82 93 93
fIN = 100 MHz 93 91
fIN = 170 MHz 87 87
fIN = 230 MHz 85 83
HD2 Second-order harmonic distortion fIN = 10 MHz 102 98 dBc
fIN = 70 MHz 82 95 93
fIN = 100 MHz 95 93
fIN = 170 MHz 87 87
fIN = 230 MHz 85 85
HD3 Third-order harmonic distortion fIN = 10 MHz 89 95 dBc
fIN = 70 MHz 83 94 94
fIN = 100 MHz 95 96
fIN = 170 MHz 92 90
fIN = 230 MHz 89 84
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 93 95 dBc
fIN = 70 MHz 86 100 95
fIN = 100 MHz 100 95
fIN = 170 MHz 99 95
fIN = 230 MHz 98 94
THD Total harmonic distortion fIN = 10 MHz 88 91 dBc
fIN = 70 MHz 76 91 89
fIN = 100 MHz 91 88
fIN = 170 MHz 85 84
fIN = 230 MHz 83 81
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –93 –92 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –91 –89
(1) Reported from a 1-MHz offset.

7.11 AC Performance: ADC3244

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3244 (fS = 125 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 72.9 73.3 dBFS
fIN = 70 MHz 71 72.6 73
fIN = 100 MHz 72.4 72.8
fIN = 170 MHz 71.7 72.2
fIN = 230 MHz 71 71.6
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.5 72.9
fIN = 70 MHz 72.2 72.6
fIN = 100 MHz 72.1 72.5
fIN = 170 MHz 71.4 71.9
fIN = 230 MHz 70.7 71.3
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –150.8 –151.1 dBFS/Hz
fIN = 70 MHz –150.5 –148.9 –150.9
fIN = 100 MHz –150.3 –150.7
fIN = 170 MHz –149.6 –150.1
fIN = 230 MHz –148.9 –149.5
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 72.8 73 dBFS
fIN = 70 MHz 69.6 72.6 72.9
fIN = 100 MHz 72.3 72.5
fIN = 170 MHz 71.5 71.9
fIN = 230 MHz 70.7 71.1
ENOB(1) Effective number of bits fIN = 10 MHz 11.8 11.8 Bits
fIN = 70 MHz 11.3 11.8 11.8
fIN = 100 MHz 11.7 11.8
fIN = 170 MHz 11.6 11.6
fIN = 230 MHz 11.5 11.5
SFDR Spurious-free dynamic range fIN = 10 MHz 93 86 dBc
fIN = 70 MHz 82 94 89
fIN = 100 MHz 89 85
fIN = 170 MHz 85 85
fIN = 230 MHz 83 82
HD2 Second-order harmonic distortion fIN = 10 MHz 95 96 dBc
fIN = 70 MHz 82 96 95
fIN = 100 MHz 91 90
fIN = 170 MHz 85 85
fIN = 230 MHz 83 83
HD3 Third-order harmonic distortion fIN = 10 MHz 94 86 dBc
fIN = 70 MHz 83 94 89
fIN = 100 MHz 91 85
fIN = 170 MHz 97 89
fIN = 230 MHz 87 85
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 100 95 dBc
fIN = 70 MHz 86 99 95
fIN = 100 MHz 99 95
fIN = 170 MHz 100 91
fIN = 230 MHz 96 92
THD Total harmonic distortion fIN = 10 MHz 91 85 dBc
fIN = 70 MHz 76 91 86
fIN = 100 MHz 87 83
fIN = 170 MHz 84 82
fIN = 230 MHz 81 80
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –97 –95 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –91 –90
(1) Reported from a 1-MHz offset.

7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 1.3 V
VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 0.4 V
IIH High-level input current RESET, SDATA, SCLK, PDN VHIGH = 1.8 V 10 µA
SEN(1) VHIGH = 1.8 V 0
IIL Low-level input current RESET, SDATA, SCLK, PDN VLOW = 0 V 0 µA
SEN VLOW = 0 V 10
DIGITAL INPUTS (SYSREFP, SYSREFM)
VIH High-level input voltage 1.3 V
VIL Low-level input voltage 0.5 V
Common-mode voltage for SYSREF 0.9 V
DIGITAL OUTPUTS, CMOS INTERFACE (SDOUT)
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0 0.1 V
DIGITAL OUTPUTS, LVDS INTERFACE
VODH High-level output differential voltage With an external 100-Ω termination 280 410 460 mV
VODL Low-level output differential voltage With an external 100-Ω termination –460 –410 –280 mV
VOCM Output common-mode voltage 1.05 V
(1) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V CMOS buffers.

7.13 Timing Requirements: General

Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C.
MIN TYP MAX UNIT
tA Aperture delay 1.24 1.44 1.64 ns
Aperture delay matching between two channels of the same device ±70 ps
Variation of aperture delay between two devices at the same temperature and supply voltage ±150 ps
tJ Aperture jitter 130 fS rms
Wake-up time Time to valid data after exiting standby power-down mode 35 65 µs
Time to valid data after exiting global power-down mode
(in this mode, both channels power down)		 85 140
ADC latency(6) 2-wire mode (default) 9 Clock cycles
1-wire mode 8
tSU_SYSREF SYSREF reference time Setup time for SYSREF referenced to input clock rising edge 1000 ps
tH_SYSREF Hold time for SYSREF referenced to input clock rising edge 100

7.14 Timing Requirements: LVDS Output

Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 7x serialization, CLOAD = 3.3 pF(2), and RLOAD = 100 Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C.(4)(1)
MIN TYP MAX UNIT
tSU Data setup time: data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM)(5)		 0.36 0.42 ns
tHO Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid(5) 0.36 0.47 ns
LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) 49%
tPDI Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over 10 MSPS < sampling frequency <
125 MSPS		 1-wire mode 2.7 4.5 6.5 ns
2-wire mode 0.44 × tS + tDELAY
tDELAY Delay time 3 4.5 5.9 ns
tFALL,
tRISE		 Data fall time, data rise time: rise time measured from –100 mV to 100 mV,
10 MSPS ≤ Sampling frequency ≤ 125 MSPS		 0.11 ns
tCLKRISE,
tCLKFALL		 Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV,
10 MSPS ≤ Sampling frequency ≤ 125 MSPS		 0.11 ns
(1) Timing parameters are ensured by design and characterization and are not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
(6) Overall latency = ADC latency + tPDI.

Table 1. LVDS Timings at Lower Sampling Frequencies: 7x Serialization (2-Wire Mode)

SAMPLING FREQUENCY (MSPS) SETUP TIME
(tSU, ns)		 HOLD TIME
(tHO, ns)
MIN TYP MAX MIN TYP MAX
25 2.27 2.6 2.41 2.6
40 1.44 1.6 1.51 1.7
50 1.2 1.32 1.24 1.4
60 0.95 1.04 0.97 1.09
80 0.68 0.75 0.72 0.81
100 0.5 0.57 0.53 0.62

Table 2. LVDS Timings at Lower Sampling Frequencies: 14x Serialization (1-Wire Mode)

SAMPLING FREQUENCY (MSPS) SETUP TIME
(tSU, ns)		 HOLD TIME
(tHO, ns)
MIN TYP MAX MIN TYP MAX
25 1.1 1.24 1.19 1.34
40 0.66 0.72 0.74 0.82
50 0.48 0.55 0.54 0.64
60 0.35 0.41 0.42 0.51
80 0.17 0.24 0.3 0.38

7.15 Typical Characteristics: ADC3241

Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3241 ADC3242 ADC3243 ADC3244 D701_SBAS671.gif
SFDR = 97.9 dBc, SNR = 73.8 dBFS, SINAD = 73.8 dBFS,
THD = 96.8 dBc, HD2 = –110.0 dBc, HD3 = –97.9 dBc
Figure 1. FFT for 10-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D703_SBAS671.gif
SFDR = 91.8 dBc, SNR = 73.4 dBFS, SINAD = 73.4 dBFS,
THD = 91.4 dBc, HD2 = –108.2 dBc, HD3 = –91.8 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D705_SBAS671.gif
SFDR = 86.6 dBc, SNR = 72.1 dBFS, SINAD = 71.9 dBFS,
THD = 84.7 dBc, HD2 = –89.8 dBc, HD3 = –86.6 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D707_SBAS671.gif
SFDR = 75.6 dBc, SNR = 69.8 dBFS, SINAD = 68.8 dBFS,
THD = 74.8 dBc, HD2 = –75.6 dBc, HD3 = –82.5 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D709_SBAS671.gif
SFDR = 68.4 dBc, SNR = 67.2 dBFS, SINAD = 67.2 dBFS,
THD = 92.6 dBc, HD2 = –68.4 dBc, HD3 = –89.5 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D711_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 82.4 dBFS,
each tone at –7 dBFS
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D713_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 78 dBFS,
each tone at –7 dBFS
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D715_SBAS671.gif
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D717_SBAS671.gif
Figure 17. Signal-to-Noise Ratio vs Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D719_SBAS671.gif
.
Figure 19. Performance vs Input Amplitude (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D721_SBAS671.gif
Figure 21. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D723_SBAS671.gif
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D725_SBAS671.gif
Figure 25. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D727_SBAS671.gif
Figure 27. Performance vs Clock Amplitude (40 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D729_SBAS671.gif
Figure 29. Performance vs Clock Duty Cycle (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D731_SBAS671.gif
RMS Noise = 1.33 LSBs
Figure 31. Idle Channel Histogram
ADC3241 ADC3242 ADC3243 ADC3244 D702_SBAS671.gif
SFDR = 89.8 dBc, SNR = 74.5 dBFS, SINAD = 74.3 dBFS,
THD = 88.3 dBc, HD2 = –89.8 dBc, HD3 = –100.3 dBc
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D704_SBAS671.gif
SFDR = 90.2 dBc, SNR = 74.1 dBFS, SINAD = 73.9 dBFS,
THD = 88.7 dBc, HD2 = –90.2 dBc, HD3 = –100.5 dBc
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D706_SBAS671.gif
SFDR = 87.7 dBc, SNR = 72.5 dBFS, SINAD = 72.3 dBFS,
THD = 85 dBc, HD2 = –87.7 dBc, HD3 = –91.2 dBc
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D708_SBAS671.gif
SFDR = 75.3 dBc, SNR = 70.0 dBFS, SINAD = 68.8 dBFS,
THD = 73.8 dBc, HD2 = –75.3 dBc, HD3 = –79.6 dBc
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D710_SBAS671.gif
SFDR = 67.9 dBc, SNR = 67.2 dBFS, SINAD = 67.2 dBFS,
THD = 87.6 dBc, HD2 = –67.9 dBc, HD3 = –96.9 dBc
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D712_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90 dBFS,
each tone at –36 dBFS
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D714_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 89 dBFS,
each tone at –36 dBFS
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D716_SBAS671.gif
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D718_SBAS671.gif
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D720_SBAS671.gif
Figure 20. Performance vs Input Amplitude (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D722_SBAS671.gif
Figure 22. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D724_SBAS671.gif
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D726_SBAS671.gif
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D728_SBAS671.gif
Figure 28. Performance vs Clock Amplitude (150 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D730_SBAS671.gif
Figure 30. Performance vs Clock Duty Cycle (150 MHz)

7.16 Typical Characteristics: ADC3242

Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3241 ADC3242 ADC3243 ADC3244 D501_SBAS671.gif
SFDR = 88.9 dBc, SFDR = 99.8 dBc (non 23), SNR = 73.6 dBFS, SINAD = 73.5 dBFS, THD = 88.8 dBc, HD2 = –111.4 dBc,
HD3 = –88.9 dBc
Figure 32. FFT for 10-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D503_SBAS671.gif
SFDR = 85.8 dBc, SFDR = 100.3 dBc (non 23),
SNR = 72.4 dBFS, SINAD = 72.2 dBFS, THD = 84.8 dBc,
HD2 = –92.3 dBc, HD3 = –85.8 dBc
Figure 34. FFT for 70-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D505_SBAS671.gif
SFDR = 85.8 dBc, SFDR = 99.1 dBc (non 23), SNR = 72.4 dBFS, SINAD = 72.2 dBFS, THD = 84.8 dBc, HD2 = –92.3 dBc,
HD3 = –85.8 dBc
Figure 36. FFT for 170-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D507_SBAS671.gif
SFDR = 74.7 dBc, SFDR = 95.2 dBc (non 23), SNR = 70.7 dBFS, SINAD = 69.3 dBFS, THD = 73.8 dBc, HD2 = –74.7 dBc,
HD3 = –81.1 dBc
Figure 38. FFT for 270-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D509_SBAS671.gif
SFDR = 68.2 dBc, SNR = 69.0 dBFS, SINAD = 69.0 dBFS,
THD = –85.7 dBc, HD2 = –68.2 dBc, HD3 = –86.5 dBc
Figure 40. FFT for 450-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D511_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 87 dBFS,
each tone at –7 dBFS
Figure 42. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D513_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 83 dBFS,
each tone at –7 dBFS
Figure 44. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D515_SBAS671.gif
Figure 46. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D517_SBAS671.gif
Figure 48. Signal-to-Noise Ratio vs Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D519_SBAS671.gif
Figure 50. Performance vs Input Amplitude (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D521_SBAS671.gif
Figure 52. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D523_SBAS671.gif
Figure 54. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D525_SBAS671.gif
Figure 56. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D527_SBAS671.gif
Figure 58. Performance vs Clock Amplitude (40 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D529_SBAS671.gif
Figure 60. Performance vs Clock Duty Cycle (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D531_SBAS671.gif
RMS Noise = 1.3 LSBs
Figure 62. Idle Channel Histogram
ADC3241 ADC3242 ADC3243 ADC3244 D502_SBAS671.gif
SFDR = 84.7 dBc, SFDR = 96.1 dBc (non 23), SNR = 74.1 dBFS, SINAD = 73.8 dBFS, THD = 83.5 dBc, HD2 = –92.2 dBc,
HD3 = –84.7 dBc
Figure 33. FFT for 10-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D504_SBAS671.gif
SFDR = 90.4 dBc, SFDR = 94.7 dBc (non 23), SNR = 73.9 dBFS, SINAD = 73.7 dBFS, THD = 87.5 dBc, HD2 = –91.9 dBc,
HD3 = –90.4 dBc
Figure 35. FFT for 70-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D506_SBAS671.gif
SFDR = 89.7 dBc, SFDR = 93 dBc (non 23), SNR = 72.9 dBFS, SINAD = 72.8 dBFS, THD = 86.6 dBc, HD2 = –89.7 dBc,
HD3 = –107.7 dBc
Figure 37. FFT for 170-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D508_SBAS671.gif
SFDR = 74.6 dBc, SFDR = 91.1 dBc (non 23), SNR = 70.9 dBFS, SINAD = 69.2 dBFS, THD = 72.9 dBc, HD2 = –74.6 dBc,
HD3 = –78.0 dBc
Figure 39. FFT for 270-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D510_SBAS671.gif
SFDR = 68.2 dBc, SNR = 69.2 dBFS, SINAD = 69.2 dBFS,
THD = –86.4 dBc, HD2 = 68.2 dBc, HD3 = –90.3 dBc
Figure 41. FFT for 450-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D512_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 88 dBFS,
each tone at –36 dBFS
Figure 43. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D514_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 85 dBFS,
each tone at –36 dBFS
Figure 45. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D516_SBAS671.gif
Figure 47. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D518_SBAS671.gif
Figure 49. Spurious-Free Dynamic Range vs
Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D520_SBAS671.gif
Figure 51. Performance vs Input Amplitude (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D522_SBAS671.gif
Figure 53. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D524_SBAS671.gif
Figure 55. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D526_SBAS671.gif
Figure 57. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D528_SBAS671.gif
Figure 59. Performance vs Clock Amplitude (150 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D530_SBAS671.gif
Figure 61. Performance vs Clock Duty Cycle (150 MHz)

7.17 Typical Characteristics: ADC3243

Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3241 ADC3242 ADC3243 ADC3244 D301_SBAS671.gif
SFDR = 88.9 dBc, SNR = 73.4 dBFS, SINAD = 73.3 dBFS,
THD = 88.8 dBc, HD2 = –109.9 dBc, HD3 = –88.9 dBc
Figure 63. FFT for 10-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D303_SBAS671.gif
SFDR = 91.3 dBc, SNR = 73.2 dBFS, SINAD = 73.1 dBFS,
THD = 91 dBc, HD2 = –109.5 dBc, HD3 = –91.3 dBc
Figure 65. FFT for 70-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D305_SBAS671.gif
SFDR = 94.9 dBc, SNR = 72.4 dBFS, SINAD = 72.4 dBFS,
THD = 93.2 dBc, HD2 = –106.1 dBc, HD3 = –94.9 dBc
Figure 67. FFT for 170-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D307_SBAS671.gif
SFDR = 75.4 dBc, SNR = 70.9 dBFS, SINAD = 69.6 dBFS,
THD = 74.3 dBc, HD2 = –75.4 dBc, HD3 = –81.0 dBc
Figure 69. FFT for 270-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D309_SBAS671.gif
SFDR = 77.8 dBc, SNR = 68.8 dBFS, SINAD = 68.3 dBFS,
THD = 77.5 dBc, HD2 = –77.8 dBc, HD3 = –91.8 dBc
Figure 71. FFT for 450-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D311_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 87 dBFS,
each tone at –7 dBFS
Figure 73. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D313_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 78.8 dBFS,
each tone at –7 dBFS
Figure 75. FFT FOR Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D315_SBAS671.gif
Figure 77. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D317_SBAS671.gif
Figure 79. Signal-to-Noise Ratio vs Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D319_SBAS671.gif
Figure 81. Performance vs Input Amplitude (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D321_SBAS671.gif
Figure 83. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D323_SBAS671.gif
Figure 85. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D325_SBAS671.gif
Figure 87. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D327_SBAS671.gif
Figure 89. Performance vs Clock Amplitude (40 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D329_SBAS671.gif
Figure 91. Performance vs Clock Duty cycle (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D331_SBAS671.gif
RMS Noise = 1.28 LSBs
Figure 93. Idle Channel Histogram
ADC3241 ADC3242 ADC3243 ADC3244 D302_SBAS671.gif
SFDR = 84.2 dBc, SNR = 73.8 dBFS, SINAD = 73.4 dBFS,
THD = 83.2 dBc, HD2 = –93.6 dBc, HD3 = –84.2 dBc
Figure 64. FFT for 10-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D304_SBAS671.gif
SFDR = 85.4 dBc, SNR = 73.6 dBFS, SINAD = 73.3 dBFS,
THD = 83.7 dBc, HD2 = –91.2 dBc, HD3 = –85.4 dBc
Figure 66. FFT for 70-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D306_SBAS671.gif
SFDR = 92.3 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,
THD = 88 dBc, HD2 = –92.3 dBc, HD3 = –95.4 dBc
Figure 68. FFT for 170-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D308_SBAS671.gif
SFDR = 75.4 dBc, SNR = 71.2 dBFS, SINAD = 69.8 dBFS,
THD = 74.2 dBc, HD2 =–75.4 dBc, HD3 = –81.2 dBc
Figure 70. FFT for 270-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D310_SBAS671.gif
SFDR = 77.8 dBc, SNR = 68.8 dBFS, SINAD = 68.3 dBFS,
THD = 77.5 dBc, HD2 = –77.8 dBc, HD3 = –91.8 dBc
Figure 72. FFT for 450-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D312_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 92.8 dBFS,
each tone at –36 dBFS
Figure 74. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D314_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 91 dBFS,
each tone at –36 dBFS
Figure 76. FFT FOR Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D316_SBAS671.gif
Figure 78. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D318_SBAS671.gif
Figure 80. Spurious-Free Dynamic Range vs
Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D320_SBAS671.gif
Figure 82. Performance vs Input Amplitude (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D322_SBAS671.gif
Figure 84. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D324_SBAS671.gif
Figure 86. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D326_SBAS671.gif
Figure 88. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D328_SBAS671.gif
Figure 90. Performance vs Clock Amplitude (150 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D330_SBAS671.gif
Figure 92. Performance vs Clock Duty Cycle (150 MHz)

7.18 Typical Characteristics: ADC3244

Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3241 ADC3242 ADC3243 ADC3244 D101_SBAS671.gif
SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,
THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc
Figure 94. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D103_SBAS671.gif
SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS,
THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc
Figure 96. FFT for 70-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D105_SBAS671.gif
SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS,
THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc
Figure 98. FFT for 170-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D107_SBAS671.gif
SFDR = 76.1 dBc, SNR = 70.8 dBFS, SINAD = 69.8 dBFS,
THD = 74.8 dBc, HD2 = –76.1 dBc, HD3 = –80.9 dBc
Figure 100. FFT for 270-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D109_SBAS671.gif
SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS,
THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc
Figure 102. FFT for 450-MHz Input Signal (Dither On)
ADC3241 ADC3242 ADC3243 ADC3244 D111_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 88.3 dBFS,
each tone at –7 dBFS
Figure 104. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D113_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86.4 dBFS,
each tone at –7 dBFS
Figure 106. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D115_SBAS671.gif
Figure 108. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D117_SBAS671.gif
Figure 110. Signal-to-Noise Ratio vs Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D119_SBAS671.gif
Figure 112. Performance vs Input Amplitude (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D121_SBAS671.gif
Figure 114. Performance vs Input Common-Mode Voltage (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D123_SBAS671.gif
Figure 116. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D125_SBAS671.gif
Figure 118. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D127_SBAS671.gif
Figure 120. Performance vs Clock Amplitude (40 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D129_SBAS671.gif
Figure 122. Performance vs Clock Duty Cycle (30 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D131_SBAS671.gif
RMS Noise = 1.4 LSBs
Figure 124. Idle Channel Histogram
ADC3241 ADC3242 ADC3243 ADC3244 D102_SBAS671.gif
SFDR = 91.8 dBc, SNR = 73.5 dBFS, SINAD = 73.4 dBFS,
THD = 87.3 dBc, HD2 = –93.8 dBc, HD3 = –91.8 dBc
Figure 95. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D104_SBAS671.gif
SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS,
THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc
Figure 97. FFT for 70-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D106_SBAS671.gif
SFDR = 89.9 dBc, SNR = 72.8 dBFS, SINAD = 72.6 dBFS,
THD = 87.1 dBc, HD2 = –97.2 dBc, HD3 = –89.9 dBc
Figure 99. FFT for 170-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D108_SBAS671.gif
SFDR = 76.1 dBc, SNR = 71.2 dBFS, SINAD = 70.2 dBFS,
THD = 74.9 dBc, HD2 = –76.1 dBc, HD3 = –81.6 dBc
Figure 101. FFT for 270-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D110_SBAS671.gif
SFDR = 75.3 dBc, SNR = 69.1 dBFS, SINAD = 67.8 dBFS,
THD = 72.7 dBc, HD2 = –76.7 dBc, HD3 = –75.3 dBc
Figure 103. FFT for 450-MHz Input Signal (Dither Off)
ADC3241 ADC3242 ADC3243 ADC3244 D112_SBAS671.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90.8 dBFS,
each tone at –36 dBFS
Figure 105. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D114_SBAS671.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 87.28 dBFS,
each tone at –36 dBFS
Figure 107. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D116_SBAS671.gif
Figure 109. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D118_SBAS671.gif
Figure 111. Spurious-Free Dynamic Range vs
Input Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D120_SBAS671.gif
Figure 113. Performance vs Input Amplitude (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D122_SBAS671.gif
Figure 115. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D124_SBAS671.gif
Figure 117. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D126_SBAS671.gif
Figure 119. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D128_SBAS671.gif
Figure 121. Performance vs Clock Amplitude (150 MHz)
ADC3241 ADC3242 ADC3243 ADC3244 D130_SBAS671.gif
Figure 123. Performance vs Clock Duty Cycle (150 MHz)

7.19 Typical Characteristics: Common

Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3241 ADC3242 ADC3243 ADC3244 D001_BAS671.gif
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Figure 125. Power-Supply Rejection Ratio vs
Test Signal Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D003_BAS671.gif
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Figure 127. Common-Mode Rejection Ratio vs
Test Signal Frequency
ADC3241 ADC3242 ADC3243 ADC3244 D009_SBAS672.gif
Figure 129. Power vs Sampling Frequency
(One-Wire Mode)
ADC3241 ADC3242 ADC3243 ADC3244 D002_BAS671.gif
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP,
SNR = 58.51 dBFS, SINAD = 58.51 dBFS, SFDR = 60.53 dBc, THD = –90.71 dBc, SFDR = 60.53 dBc (non 23)
Figure 126. Power-Supply Rejection Ratio Spectrum
ADC3241 ADC3242 ADC3243 ADC3244 D004_BAS671.gif
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP,
SNR = 69.72 dBFS, SINAD = 69.66 dBFS, SFDR = 75.66 dBc, THD = –86.98 dBc, SFDR = 75.66 dBc (non 23)
Figure 128. Common-Mode Rejection Ratio Spectrum

7.20 Typical Characteristics: Contour

Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when is chopper enabled, unless otherwise noted.
ADC3241 ADC3242 ADC3243 ADC3244 SFDR_BAS671.png Figure 130. Spurious-Free Dynamic Range (SFDR)
ADC3241 ADC3242 ADC3243 ADC3244 SNR_BAS671.png Figure 131. Signal-to-Noise Ratio (SNR)