SNAS747 June   2017 ADC081S101-MIL

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Determining Throughput
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC081S101-MIL Transfer Function
      2. 8.4.2 Modes Of Operation
        1. 8.4.2.1 Normal Mode
        2. 8.4.2.2 Shutdown Mode
  9. 9 Applications Information
    1. 9.1 Analog Input
      1. 9.1.1 Digital Inputs And Outputs
    2. 9.2 Typical Application Circuit
  10. 10Power Supply Recommendations
    1. 10.1 Noise Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

DBV or NGF Package
6-Lead SOT-23 or WSON
Top View
ADC081S101-MIL 20145705.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
ANALOG I/O
3 VIN I Analog input. This signal can range from 0 V to VA.
DIGITAL I/O
4 SCLK I Digital clock input. This clock directly controls the conversion and readout processes.
5 SDATA O Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.
6 CS I Chip select. On the falling edge of CS, a conversion process begins.
POWER SUPPLY
1 VA P Positive supply pin. This pin should be connected to a quiet +2.7-V to +5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin.
2 GND G The ground return for the supply and signals.
PAD GND G For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground.