SNAS308G April   2005  – May 2016 ADC081S021

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Determining Throughput
    4. 8.4 Device Functional Modes
      1. 8.4.1 Transfer Function
      2. 8.4.2 Modes of Operation
        1. 8.4.2.1 Normal Mode
        2. 8.4.2.2 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Inputs
      2. 9.1.2 Digital Inputs and Outputs
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Noise Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Analog supply voltage, VA –0.3 6.5 V
Voltage on any analog pin to GND –0.3 VA + 0.3 V
Voltage on any digital pin to GND –0.3 6.5 V
Input current at any pin(4) ±10 mA
Package input current(4) ±20 mA
Power consumption at TA = 25°C See(5)
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the TI Office/Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin must be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. These specifications do not apply to the VA pin. The current into the VA pin is limited by the analog supply voltage specification.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation listed above is reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions must always be avoided.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±3500 V
Machine model (MM) ±300
(1) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VA Supply voltage 2.7 5.25 V
Digital input pins voltage (regardless of supply voltage) –0.3 5.25 V
Analog input pins voltage 0 VA V
Clock frequency 25 20000 kHz
Sample rate 1 Msps
TA Operating temperature –40 85 °C
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

7.4 Thermal Information

THERMAL METRIC(1) ADC081S021 UNIT
DBV (SOT-23) NGF (WSON)
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 184.5 99.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 151.2 118.3 °C/W
RθJB Junction-to-board thermal resistance 29.7 68.9 °C/W
ψJT Junction-to-top characterization parameter 29.8 6.6 °C/W
ψJB Junction-to-board characterization parameter 29.1 69.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 14.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical values correspond to TA = 25°C, and minimum and maximum limits apply over –40°C to 85°C operating temperature range (unless otherwise noted). VA = 2.7 V to 5.25 V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 15 pF (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN(2) TYP MAX(2) UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with
no missing codes		 8 Bits
INL Integral non-linearity VA = 2.7 V to 3.6 V ±0.03 ±0.3 LSB
VA = 4.75 V to 5.25 V TA = 25°C –0.03 0.04 LSB
TA = –40°C to 85°C ±0.3 ±0.3
DNL Differential non-linearity VA = 2.7 V to 3.6 V ±0.03 ±0.2 LSB
VA = 4.75 V to 5.25 V TA = 25°C –0.03 0.04 LSB
TA = –40°C to 85°C ±0.2 ±0.2
VOFF Offset error VA = 2.7 V to 3.6 V –0.01 ±0.2 LSB
VA = 4.75 V to 5.25 V 0.03 ±0.2 LSB
GE Gain error VA = 2.7 V to 3.6 V 0.04 ±0.4 LSB
VA = 4.75 V to 5.25 V 0.1 ±0.4 LSB
TUE Total unadjusted error VA = 2.7 V to 3.6 V TA = 25°C –0.065 0.055 LSB
TA = –40°C to 85°C ±0.3 ±0.3
VA = 4.75 V to 5.25 V TA = 25°C –0.06 0.03 LSB
TA = –40°C to 85°C ±0.3 ±0.3
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-noise
plus distortion ratio		 VA = 2.7 V to 5.25 V, fIN = 100 kHz,
–0.02 dBFS		 49 49.5 dBFS
SNR Signal-to-noise ratio VA = 2.7 V to 5.25 V, fIN = 100 kHz,
–0.02 dBFS		 49 49.6 dBFS
THD Total harmonic distortion VA = 2.7 V to 5.25 V, fIN = 100 kHz,
–0.02 dBFS		 –77 –65 dBFS
SFDR Spurious-free dynamic range VA = 2.7 V to 5.25 V, fIN = 100 kHz,
–0.02 dBFS		 65 68 dBFS
ENOB Effective number of bits VA = 2.7 V to 5.25 V, fIN = 100 kHz,
–0.02 dBFS		 7.8 7.9 Bits
IMD Intermodulation distortion,
second order terms		 VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –83 dBFS
Intermodulation distortion,
third order terms		 VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –82 dBFS
FPBW –3 dB full power bandwidth VA = 5 V 11 MHz
VA = 3 V 8 MHz
ANALOG INPUT CHARACTERISTICS
VIN Input range 0 to VA V
IDCL DC leakage current ±1 µA
CINA Input capacitance Track mode 30 pF
Hold mode 4 pF
DIGITAL INPUT CHARACTERISTICS
VIH Input high voltage VA = 5.25 V 2.4 V
VA = 3.6 V 2.1 V
VIL Input low voltage VA = 5 V 0.8 V
VA = 3 V 0.4 V
IIN Input current VIN = 0 V or VA ±0.1 ±1 µA
CIND Digital input capacitance 2 4 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH Output high voltage ISOURCE = 200 µA VA – 0.2 VA – 0.07 V
ISOURCE = 1 mA VA – 0.1 V
VOL Output low voltage ISINK = 200 µA 0.03 0.4 V
ISINK = 1 mA 0.1 V
IOZH, IOZL TRI-STATE leakage current ±0.1 ±10 µA
COUT TRI-STATE output capacitance 2 4 pF
Output coding Straight (natural) binary
POWER SUPPLY CHARACTERISTICS
VA Supply voltage 2.7 5.25 V
IA Supply current, normal mode
(operational, CS low)		 VA = 5.25 V, fSAMPLE = 200 ksps 1.47 2.2 mA
VA = 3.6 V, fSAMPLE = 200 ksps 0.36 0.9 mA
Supply current, shutdown
(CS high)		 fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 500 nA
VA = 5.25 V, fSCLK = 4 MHz, fSAMPLE = 0 ksps 60 µA
PD Power consumption, normal mode
(operational, CS low)		 VA = 5.25 V 7.7 11.6 mW
VA = 3.6 V 1.3 3.24 mW
Power consumption, shutdown
(CS high)		 fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 2.6 µW
fSCLK = 4 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 315 µW
AC ELECTRICAL CHARACTERISTICS
fSCLK Clock frequency See(3) 1 4 MHz
fS Sample rate See(3) 50 200 ksps
tHOLD Hold time, falling edge 13 SCLK
DC SCLK duty cycle fSCLK = 4 MHz 40% 50% 60%
tACQ Minimum time required for acquisition 350 ns
tQUIET Quiet time See(4) 50 ns
tAD Aperture delay 3 ns
tAJ Aperture jitter 30 ps
(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(2) Data sheet minimum and maximum specification limits are specified by design, test, or statistical analysis.
(3) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is specified under Operating Ratings.
(4) Minimum quiet time required by bus relinquish and the start of the next conversion.

7.6 Timing Requirements

The following specifications apply for VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 1.0 MHz to 4.0 MHz, CL = 25 pF, fSAMPLE = 50 ksps to 200 ksps, and TA = –40°C to 85°C (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tCS Minimum CS pulse width 10 ns
tCSSU CS setup time prior to SCLK falling edge 10 ns
tCSH CS hold time after SCLK falling edge 1 ns
tEN Delay from CS until SDATA TRI-STATE disabled(2) 20 ns
tACC Data access time after SCLK falling edge(3) VA = 2.7 V to 3.6 V 40 ns
VA = 4.75 V to 5.25 V 20 ns
tCL SCLK low pulse width 0.4 × tSCLK ns
tCH SCLK high pulse width 0.4 × tSCLK ns
tH SCLK to data valid hold time VA = 2.7 V to 3.6 V 7 ns
VA = 4.75 V to 5.25 V 5 ns
tDIS SCLK falling edge to SDATA high impedance(4) VA = 2.7 V to 3.6 V 6 25 ns
VA = 4.75 V to 5.25 V 5 25 ns
tPOWER-UP Power-up time from full power down TA = 25°C 1 µs
(1) Data sheet minimum and maximum specification limits are specified by design, test, or statistical analysis.
(2) Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V.
(3) Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V or 2 V.
(4) tDIS is derived from the time taken by the outputs to change by 0.5 V with the timing test circuit. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading.
ADC081S021 20145408.gif Figure 1. Timing Test Circuit
ADC081S021 20145406.gif Figure 2. Serial Timing Diagram
ADC081S021 20145412.gif Figure 3. SCLK and CS Timing Parameters

7.7 Typical Characteristics

TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz (unless otherwise noted)
ADC081S021 20145420.png Figure 4. DNL fSCLK = 1 MHz
ADC081S021 20145460.png Figure 6. DNL fSCLK = 4 MHz
ADC081S021 20145465.png Figure 8. DNL vs Clock Frequency
ADC081S021 20145467.png Figure 10. Total Unadjusted Error vs Clock Frequency
VA = 3 V or 5 V
ADC081S021 20145464.png Figure 12. SINAD vs Clock Frequency
ADC081S021 20145468.png Figure 14. THD vs Clock Frequency
ADC081S021 20145470.png Figure 16. Spectral Response, VA = 5 V
fSCLK = 4 MHz
ADC081S021 20145421.png Figure 5. INL fSCLK = 1 MHz
ADC081S021 20145461.png Figure 7. INL fSCLK = 4 MHz
ADC081S021 20145466.png Figure 9. INL vs Clock Frequency
ADC081S021 20145463.png Figure 11. SNR vs Clock Frequency
ADC081S021 20145472.png Figure 13. SFDR vs Clock Frequency
ADC081S021 20145469.png Figure 15. Spectral Response, VA = 5 V
fSCLK = 1 MHz
ADC081S021 20145455.png Figure 17. Power Consumption vs Throughput
fSCLK = 4 MHz