SPRS439N June 2007  – October 2016 TMS320F28232 , TMS320F28234 , TMS320F28235 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335

PRODUCTION DATA. 

  1. 1 Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings - Automotive
    3. 5.3 ESD Ratings - Commercial
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Consumption Summary
      1. 5.5.1Reducing Current Consumption
      2. 5.5.2Current Consumption Graphs
    6. 5.6 Electrical Characteristics
    7. 5.7 Thermal Resistance Characteristics
      1. 5.7.1PGF Package
      2. 5.7.2PTP Package
      3. 5.7.3ZHH Package
      4. 5.7.4ZJZ Package
    8. 5.8 Thermal Design Considerations
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1Timing Parameter Symbology
        1. 5.9.1.1General Notes on Timing Parameters
        2. 5.9.1.2Test Load Circuit
        3. 5.9.1.3Device Clock Table
      2. 5.9.2Power Sequencing
        1. 5.9.2.1Power Management and Supervisory Circuit Solutions
      3. 5.9.3Clock Requirements and Characteristics
      4. 5.9.4Peripherals
        1. 5.9.4.1General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
          2. 5.9.4.1.2 GPIO - Input Timing
          3. 5.9.4.1.3Sampling Window Width for Input Signals
          4. 5.9.4.1.4Low-Power Mode Wakeup Timing
        2. 5.9.4.2Enhanced Control Peripherals
          1. 5.9.4.2.1Enhanced Pulse Width Modulator (ePWM) Timing
          2. 5.9.4.2.2Trip-Zone Input Timing
          3. 5.9.4.2.3High-Resolution PWM Timing
          4. 5.9.4.2.4Enhanced Capture (eCAP) Timing
          5. 5.9.4.2.5Enhanced Quadrature Encoder Pulse (eQEP) Timing
          6. 5.9.4.2.6ADC Start-of-Conversion Timing
        3. 5.9.4.3External Interrupt Timing
        4. 5.9.4.4I2C Electrical Specification and Timing
        5. 5.9.4.5Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1Master Mode Timing
          2. 5.9.4.5.2SPI Slave Mode Timing
        6. 5.9.4.6Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1McBSP Transmit and Receive Timing
          2. 5.9.4.6.2McBSP as SPI Master or Slave Timing
      5. 5.9.5Emulator Connection Without Signal Buffering for the DSP
      6. 5.9.6External Interface (XINTF) Timing
        1. 5.9.6.1USEREADY = 0
        2. 5.9.6.2Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5External Interface Read Timing
        6. 5.9.6.6External Interface Write Timing
        7. 5.9.6.7External Interface Ready-on-Read Timing With One External Wait State
        8. 5.9.6.8External Interface Ready-on-Write Timing With One External Wait State
        9. 5.9.6.9 XHOLD and XHOLDA Timing
      7. 5.9.7Flash Timing
    10. 5.10On-Chip Analog-to-Digital Converter
      1. 5.10.1ADC Power-Up Control Bit Timing
      2. 5.10.2Definitions
      3. 5.10.3Sequential Sampling Mode (Single-Channel) (SMODE = 0)
      4. 5.10.4Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
      5. 5.10.5Detailed Descriptions
    11. 5.11Migrating Between F2833x Devices and F2823x Devices
  6. 6Detailed Description
    1. 6.1Brief Descriptions
      1. 6.1.1 C28x CPU
      2. 6.1.2 Memory Bus (Harvard Bus Architecture)
      3. 6.1.3 Peripheral Bus
      4. 6.1.4 Real-Time JTAG and Analysis
      5. 6.1.5 External Interface (XINTF)
      6. 6.1.6 Flash
      7. 6.1.7 M0, M1 SARAMs
      8. 6.1.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
      9. 6.1.9 Boot ROM
        1. 6.1.9.1Peripheral Pins Used by the Bootloader
      10. 6.1.10Security
      11. 6.1.11Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12External Interrupts (XINT1-XINT7, XNMI)
      13. 6.1.13Oscillator and PLL
      14. 6.1.14Watchdog
      15. 6.1.15Peripheral Clocking
      16. 6.1.16Low-Power Modes
      17. 6.1.17Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.1932-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20Control Peripherals
      21. 6.1.21Serial Port Peripherals
    2. 6.2Peripherals
      1. 6.2.1 DMA Overview
      2. 6.2.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3 Enhanced PWM Modules
      4. 6.2.4 High-Resolution PWM (HRPWM)
      5. 6.2.5 Enhanced CAP Modules
      6. 6.2.6 Enhanced QEP Modules
      7. 6.2.7 Analog-to-Digital Converter (ADC) Module
        1. 6.2.7.1ADC Connections if the ADC Is Not Used
        2. 6.2.7.2ADC Registers
        3. 6.2.7.3ADC Calibration
      8. 6.2.8 Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11Serial Peripheral Interface (SPI) Module (SPI-A)
      12. 6.2.12Inter-Integrated Circuit (I2C)
      13. 6.2.13GPIO MUX
      14. 6.2.14External Interface (XINTF)
    3. 6.3Memory Maps
    4. 6.4Register Map
      1. 6.4.1Device Emulation Registers
    5. 6.5Interrupts
      1. 6.5.1External Interrupts
    6. 6.6System Control
      1. 6.6.1OSC and PLL Block
        1. 6.6.1.1External Reference Oscillator Clock Option
        2. 6.6.1.2PLL-Based Clock Module
        3. 6.6.1.3Loss of Input Clock
      2. 6.6.2Watchdog Block
    7. 6.7Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1Getting Started
    2. 8.2Device and Development Support Tool Nomenclature
    3. 8.3Tools and Software
    4. 8.4Documentation Support
    5. 8.5Related Links
    6. 8.6Community Resources
    7. 8.7Trademarks
    8. 8.8Electrostatic Discharge Caution
    9. 8.9Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1Packaging Information

1 Device Overview

1.1 Features

  • High-Performance Static CMOS Technology
    • Up to 150 MHz (6.67-ns Cycle Time)
    • 1.9-V/1.8-V Core, 3.3-V I/O Design
  • High-Performance 32-Bit CPU (TMS320C28x)
    • IEEE 754 Single-Precision Floating-Point Unit (FPU) (F2833x Only)
    • 16 × 16 and 32 × 32 MAC Operations
    • 16 × 16 Dual MAC
    • Harvard Bus Architecture
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
    • Code-Efficient (in C/C++ and Assembly)
  • Six-Channel DMA Controller (for ADC, McBSP, ePWM, XINTF, and SARAM)
  • 16-Bit or 32-Bit External Interface (XINTF)
    • More Than 2M × 16 Address Reach
  • On-Chip Memory
    • F28335, F28333, F28235:
      256K × 16 Flash, 34K × 16 SARAM
    • F28334, F28234:
      128K × 16 Flash, 34K × 16 SARAM
    • F28332, F28232:
      64K × 16 Flash, 26K × 16 SARAM
    • 1K × 16 OTP ROM
  • Boot ROM (8K × 16)
    • With Software Boot Modes (Through SCI, SPI, CAN, I2C, McBSP, XINTF, and Parallel I/O)
    • Standard Math Tables
  • Clock and System Control
    • On-Chip Oscillator
    • Watchdog Timer Module
  • GPIO0 to GPIO63 Pins Can Be Connected to One of the Eight External Core Interrupts
  • Peripheral Interrupt Expansion (PIE) Block That Supports All 58 Peripheral Interrupts
  • 128-Bit Security Key/Lock
    • Protects Flash/OTP/RAM Blocks
    • Prevents Firmware Reverse Engineering
  • Enhanced Control Peripherals
    • Up to 18 PWM Outputs
    • Up to 6 HRPWM Outputs With 150 ps MEP Resolution
    • Up to 6 Event Capture Inputs
    • Up to 2 Quadrature Encoder Interfaces
    • Up to 8 32-Bit Timers
      (6 for eCAPs and 2 for eQEPs)
    • Up to 9 16-Bit Timers
      (6 for ePWMs and 3 XINTCTRs)
  • Three 32-Bit CPU Timers
  • Serial Port Peripherals
    • Up to 2 CAN Modules
    • Up to 3 SCI (UART) Modules
    • Up to 2 McBSP Modules (Configurable as SPI)
    • One SPI Module
    • One Inter-Integrated Circuit (I2C) Bus
  • 12-Bit ADC, 16 Channels
    • 80-ns Conversion Rate
    • 2 × 8 Channel Input Multiplexer
    • Two Sample-and-Hold
    • Single/Simultaneous Conversions
    • Internal or External Reference
  • Up to 88 Individually Programmable, Multiplexed GPIO Pins With Input Filtering
  • JTAG Boundary Scan Support
    • IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Real-Time Debug Using Hardware
  • Development Support Includes
    • ANSI C/C++ Compiler/Assembler/Linker
    • Code Composer Studio™ IDE
    • DSP/BIOS™ and SYS/BIOS
    • Digital Motor Control and Digital Power Software Libraries
  • Low-Power Modes and Power Savings
    • IDLE, STANDBY, HALT Modes Supported
    • Disable Individual Peripheral Clocks
  • Endianness: Little Endian
  • Package Options:
    • Lead-free, Green Packaging
    • Plastic Ball Grid Array (BGA) (ZJZ)
    • MicroStar BGA™ (ZHH)
    • Low-Profile Quad Flatpack (LQFP) (PGF)
    • Thermally Enhanced Low-Profile Quad Flatpack (HLQFP) (PTP)
  • Temperature Options:
    • A: –40°C to 85°C (PGF, ZHH, ZJZ)
    • S: –40°C to 125°C (PTP, ZJZ)
    • Q: –40°C to 125°C (PTP, ZJZ)
      (AEC Q100 Qualification for Automotive Applications)

1.2 Applications

  • Industrial AC Inverter Drives
  • Industrial Servo Amplifiers and Controllers
  • Computer Numerical Control (CNC) Machining
  • Uninterruptible and Server Power Supplies
  • Telecom Equipment Power
  • Solar Inverters

1.3 Description

The TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices, members of the TMS320C28x/Delfino™ DSC/MCU generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, the devices are abbreviated as F28335, F28334, F28333, F28332, F28235, F28234, and F28232, respectively. Table 3-1 and Table 3-2 provide a summary of features for each device.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE
TMS320F28335ZHHBGA MicroStar (179)12.0 mm × 12.0 mm
TMS320F28334ZHHBGA MicroStar (179)12.0 mm × 12.0 mm
TMS320F28332ZHHBGA MicroStar (179)12.0 mm × 12.0 mm
TMS320F28235ZHHBGA MicroStar (179)12.0 mm × 12.0 mm
TMS320F28234ZHHBGA MicroStar (179)12.0 mm × 12.0 mm
TMS320F28232ZHHBGA MicroStar (179)12.0 mm × 12.0 mm
TMS320F28335ZJZBGA (176)15.0 mm × 15.0 mm
TMS320F28334ZJZBGA (176)15.0 mm × 15.0 mm
TMS320F28332ZJZBGA (176)15.0 mm × 15.0 mm
TMS320F28235ZJZBGA (176)15.0 mm × 15.0 mm
TMS320F28234ZJZBGA (176)15.0 mm × 15.0 mm
TMS320F28232ZJZBGA (176)15.0 mm × 15.0 mm
TMS320F28335PGFLQFP (176)24.0 mm × 24.0 mm
TMS320F28334PGFLQFP (176)24.0 mm × 24.0 mm
TMS320F28333PGFLQFP (176)24.0 mm × 24.0 mm
TMS320F28332PGFLQFP (176)24.0 mm × 24.0 mm
TMS320F28235PGFLQFP (176)24.0 mm × 24.0 mm
TMS320F28234PGFLQFP (176)24.0 mm × 24.0 mm
TMS320F28232PGFLQFP (176)24.0 mm × 24.0 mm
TMS320F28335PTPHLQFP (176)24.0 mm × 24.0 mm
TMS320F28334PTPHLQFP (176)24.0 mm × 24.0 mm
TMS320F28332PTPHLQFP (176)24.0 mm × 24.0 mm
TMS320F28235PTPHLQFP (176)24.0 mm × 24.0 mm
TMS320F28234PTPHLQFP (176)24.0 mm × 24.0 mm
TMS320F28232PTPHLQFP (176)24.0 mm × 24.0 mm
(1) For more information on these devices, see Section 9, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 fbd_indus_prs439.gif
Figure 1-1 Functional Block Diagram