产品详情

DSP type 1 C64x DSP (max) (MHz) 594 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
DSP type 1 C64x DSP (max) (MHz) 594 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
NFBGA (ZWT) 361 256 mm² 16 x 16
  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 594-MHz C64x+™ Clock Rate
    • 297-MHz ARM926EJ-S™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752 C64x+ MIPS
    • Fully Software-Compatible With C64x /ARM9™
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S (MPU) Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 16K-Byte ROM
  • Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Processing Subsystem
    • Resize Engine Provides:
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • 4 - 54 MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-Bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O)
    • Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • CompactFlash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Port Interface (SPI) with Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480 Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All trademarks are the property of their respective owners.

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 594-MHz C64x+™ Clock Rate
    • 297-MHz ARM926EJ-S™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752 C64x+ MIPS
    • Fully Software-Compatible With C64x /ARM9™
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S (MPU) Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 16K-Byte ROM
  • Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Processing Subsystem
    • Resize Engine Provides:
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • 4 - 54 MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-Bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O)
    • Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • CompactFlash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Port Interface (SPI) with Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480 Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All trademarks are the property of their respective owners.

The TMS320DM6443 (also referenced as DM6443) leverages TI's Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units&151;two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320DM6443 (also referenced as DM6443) leverages TI's Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units&151;two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320DM6443 Digital Media System-on-Chip 数据表 (Rev. G) 2010年 8月 30日
* 勘误表 TMS320DM6443 Digital Media SoC Silicon Errata (Revs 2.3, 2.1, 1.3, 1.2, 1.1) (Rev. N) 2010年 8月 12日
应用手册 高速接口布局指南 (Rev. J) PDF | HTML 英语版 (Rev.J) PDF | HTML 2023年 3月 23日
应用手册 构建小型嵌入式Linux 内核示例 (Rev. A) 英语版 (Rev.A) 2013年 7月 30日
用户指南 TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012年 8月 21日
用户指南 TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012年 8月 21日
用户指南 Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012年 8月 9日
应用手册 Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
用户指南 TMS320DM644x DMSoC 64-bit Timer User's Guide 2011年 8月 1日
用户指南 TMS320C6000 Programmer's Guide (Rev. K) 2011年 7月 11日
用户指南 TMS320DM644x DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide (Rev. F) 2011年 3月 25日
用户指南 TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (Rev. D) 2011年 1月 27日
用户指南 TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (Rev. E) 2011年 1月 12日
用户指南 TMS320DM644x DMSoC EMAC/MDIO Module User's Guide (Rev. B) 2010年 12月 23日
用户指南 TMS320DM644x DMSoC Video Processing Front End (VPFE) User's Guide (Rev. H) 2010年 8月 25日
用户指南 TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 2010年 8月 19日
应用手册 TMS320DM6446/3 Power Consumption Summary (Rev. B) 2010年 8月 16日
用户指南 TMS320DM644x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. A) 2010年 8月 6日
用户指南 TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 2010年 8月 3日
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010年 7月 30日
用户指南 TMS320DM644x DMSoC ARM Subsystem Reference Guide (Rev. C) 2010年 7月 21日
应用手册 Migrating From TMS320DM644x v.2.1 ROM Bootloader to 2.3 Version 2010年 7月 20日
用户指南 TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (Rev. G) 2010年 6月 2日
用户指南 TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 2010年 3月 18日
用户指南 TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 2010年 3月 18日
应用手册 USB Compliance Checklist (Rev. A) 2010年 3月 10日
应用手册 Booting and Flashing via the DaVinci TMS320DM644x Serial Interface (Rev. A) 2009年 9月 10日
应用手册 LSP 2.10 DaVinci Linux Drivers (Rev. A) 2009年 7月 8日
应用手册 常用对象文件格式 (COFF) 2009年 4月 15日
用户指南 TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. C) 2009年 2月 24日
用户指南 TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide (Rev. B) 2009年 2月 22日
用户指南 TMS320C64x+ DSP Cache User's Guide (Rev. B) 2009年 2月 11日
应用手册 Booting DaVinci EVM from NAND Flash (Rev. A) 2008年 12月 15日
应用手册 5 VIN solution using DCDC Controllers, a LDO, and a Digitally Prog. Sequencer 2008年 11月 24日
应用手册 Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 2008年 8月 21日
更多文献资料 达芬奇技术概述手册 (Rev. B) 英语版 (Rev.B) 2008年 8月 12日
应用手册 Understanding the Davinci Preview Engine (Rev. A) 2008年 7月 23日
应用手册 Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日
应用手册 Understanding the Davinci Resizer (Rev. B) 2008年 7月 17日
应用手册 Implementing the DDR2 PCB Layout on the TMS320DM644x DMSoC (Rev. G) 2008年 6月 16日
用户指南 TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller UG (Rev. D) 2008年 5月 27日
用户指南 TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 2008年 5月 15日
用户指南 TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 2008年 5月 15日
用户指南 TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 2008年 5月 5日
应用手册 TMS320DM644x Thermal Considerations (Rev. A) 2008年 4月 23日
应用手册 TMS320DM6441 Power Consumption Summary Application Report 2008年 4月 8日
用户指南 TMS320DM644x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) 2008年 4月 8日
用户指南 TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 2008年 3月 6日
用户指南 TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (Rev. D) 2008年 2月 25日
用户指南 TMS320DM644x DMSoC VLYNQ Port User's Guide (Rev. A) 2007年 9月 20日
用户指南 TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide (Rev. B) 2007年 9月 17日
应用手册 Running Demo via ddd on the DVEVM 2007年 7月 30日
应用手册 Using Static IP Between Linux Host and the DVEVM 2007年 7月 30日
应用手册 Compact Flash (CF) Support on the DVEVM 2007年 7月 25日
应用手册 Host USB Support on the DVEVM 2007年 7月 20日
应用手册 Decode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 2007年 6月 27日
应用手册 Digital Video Using DaVinci SoC 2007年 6月 27日
应用手册 Encode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 2007年 6月 27日
应用手册 EncodeDecode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 2007年 6月 27日
用户指南 TMS320DM644x DMSoC Peripherals Overview Reference Guide (Rev. C) 2007年 4月 18日
产品概述 TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007年 4月 4日
EVM 用户指南 TMS320DM644x DVEVM Windows CE v5.0 BSP Codec Engine User’s Guide 2007年 3月 23日
EVM 用户指南 TMS320DM644x DVEVM Windows CE v5.0 Codec Engine Binary User's Guide 2007年 3月 23日
产品概述 DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 2007年 2月 13日
更多文献资料 Overview of DaVinci™ TMS320DM644x Digital Media Portfolio (Rev. B) 2007年 2月 13日
用户指南 TMS320DM644x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. A) 2007年 2月 7日
应用手册 Basic Application Loading over the Serial Interface for the DaVinci TMS320DM644x 2006年 12月 21日
产品概述 Portable Media Player Based on DaVinci Technology 2006年 11月 14日
产品概述 Universal IP Player Solution from ATEME 2006年 11月 2日
应用手册 DaVinci System Level Benchmarking Measurements 2006年 9月 28日
产品概述 DaVinci Benchmarks Product Bulletin (Rev. A) 2006年 9月 12日
应用手册 Fast Development with DaVinci On Screen Display (OSD) 2006年 7月 6日
用户指南 TMS320C64x+ DSP Big-Endian Library Programmer's Reference 2006年 3月 10日
用户指南 TMS320C64x+ Image/Video Processing Library Programmer's Reference 2006年 3月 10日
应用手册 Migrating from EDMA v2.0 to EDMA v3.0 for TMS320DM644X DMSoC 2005年 12月 3日
用户指南 TMS320DM644x DMSoC ATA Controller User's Guide 2005年 12月 3日
用户指南 TMS320DM644x DMSoC DSP Subsystem Reference Guide 2005年 12月 3日
应用手册 Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005年 10月 20日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

调试探针

TMDSADP — 自适应时钟 JTAG 仿真适配器

TMDSADP1420 适配器 – 可将带有 14 引脚本机连接器的 TI 和第三方 XDS510 和 XDS560 类仿真器连接到带有紧凑型 (CTI) 20 引脚接头的 TMDXEVM6446 或客户电路板上。该适配器可改善信号完整性、转换电压,并可以选择提供自适应时钟。

TMDSADP1414 – 可将 TI 和第三方 XDS510 和 XDS560 类 14 引脚仿真器连接到带有 14 引脚 JTAG 接头的定制客户电路板。TMDSADP1414 适配器可改善信号完整性、转换电压,并可以选择提供自适应时钟。它与 TI 和第三方 XDS510 和 XDS560 (...)

用户指南: PDF
调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针(仿真器)。与低成本的 XDS110 和高性能的 XDS560v2 相比,XDS200 在低成本和高性能之间实现了平衡;并在单个仓体中支持广泛的标准(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪,则需要使用 XDS560v2 PRO TRACE

XDS200 通过 TI 20 引脚连接器(带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

TI.com 上无现货
软件开发套件 (SDK)

LINUXDVSDK-DV — Linux 数字视频软件开发套件 (DVSDK) v2x/v3x - 达芬奇数字媒体处理器

2010 年 10 月生效 - Linux DVSDK v4 已发布。对于上面未列出的 DaVinci™ 器件,请在 TI.com 上搜索您的器件型号;此产品页面将提供指向您当前 DVSDK 的链接。

借助 Linux™ 数字视频软件开发套件 (DVSDK),DaVinci 系统集成人员能快速开发可在 DaVinci 系列不同器件间轻松移植的 Linux 多媒体应用。每个 DVSDK 都包含一套预先测试的操作系统、应用框架和具有示例程序的编解码器库,这些示例程序演示了从外设流入和流出音频和视频数据的实时解码和编码过程。对于配备 DSP 内核的 DaVinci 器件,DVSDK (...)

应用软件和框架

TMDMFP — 多媒体框架产品 (MFP) - 编解码器引擎,框架组件和 xDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable DSPs over fixed-function devices is their ability to accelerate multiple multimedia functions in a single device. TI multimedia framework products are designed to enable users to easily share a DSP between algorithms by handling (...)

用户指南: PDF
驱动程序或库

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
SM320C6201-EP 增强型产品 C6201 定点 DSP SM320C6455-EP 增强型产品 C6455 定点 DSP SMJ320C6201B 军用定点数字信号处理器 SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 定点数字信号处理器 TMS320C6205 定点数字信号处理器 TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6412 C64x 定点 DSP- 高达 720MHz、McBSP、McASP、I2cC、以太网 TMS320C6414 C64x 定点 DSP - 高达 720MHz、McBSP TMS320C6414T C64x 定点 DSP - 高达 1GHz、McBSP TMS320C6415 C64x 定点 DSP - 高达 720MHz、McBSP、PCI TMS320C6415T C64x 定点 DSP - 高达 850MHz、McBSP、PCI TMS320C6416 C64x 定点 DSP - 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6416T C64x 定点 DSP - 高达 850MHz、McBSP、PCI、VCP/TCP TMS320C6421 C64x+ 定点 DSP - 高达 600MHz、8 位 EMIFA、16 位 DDR2、SDRAM TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424 C64x+ 定点 DSP - 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2、SDRAM TMS320C6424Q C64x+ 定点 DSP - 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6452 C64x+ 定点 DSP- 高达 900MHz、1Gbps 以太网 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 C64x+ 频率高达 1.2GHz、具有 64 位 EMIFA、32 位和 16 位 DDR2、1Gbps 以太网的定点 DSP TMS320C6457 通信基础设施数字信号处理器 TMS320C6474 多核数字信号处理器 TMS320DM640 视频/成像定点数字信号处理器 TMS320DM641 视频/成像定点数字信号处理器 TMS320DM642 视频/成像定点数字信号处理器 TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431 数字媒体处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6433 数字媒体处理器 TMS320DM6435 数字媒体处理器 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437 数字媒体处理器 TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6443 达芬奇数字媒体片上系统 TMS320DM6446 达芬奇数字媒体片上系统
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
软件编解码器

C64XPLUSCODECS — 编解码器 - 视频和语音 - 基于 C64x+ 的器件(OMAP35x、C645x、C647x、DM646、DM644x 和 DM643x)

TI 编解码器免费提供,附带生产许可且现在可供下载。所有编解码器均经过生产环境测试,可轻松集成到视频和语音应用中。点击“获取软件”按钮(上方),获取经过测试的最新编解码器版本。该页面及每个安装程序中都包含有数据表和发布说明。

其他信息:

软件编解码器

DM644XCODECS 用于 DM644x 的编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
SM320DM6446-HIREL 高可靠性产品数字媒体 DM6446 处理器 TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6443 达芬奇数字媒体片上系统 TMS320DM6446 达芬奇数字媒体片上系统
下载选项
软件编解码器

TMDXDAISXDM — eXpressDSP 算法标准 – xDAIS 开发者套件和 xDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

用户指南: PDF
仿真模型

DM6443 ZWT BSDL Model

SPRM204.ZIP (10 KB) - BSDL Model
仿真模型

DM6443 ZWT BSDL version 2.1 Model (Rev. A)

SPRM326A.ZIP (8 KB) - BSDL Model
仿真模型

DM6443 ZWT IBIS Model

SPRM199.ZIP (112 KB) - IBIS Model
封装 引脚 CAD 符号、封装和 3D 模型
NFBGA (ZWT) 361 Ultra Librarian

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

视频