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TLK3132

最晚可采购期限

2 通道 600Mbps 至 3.75Gbps 多速率收发器

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TLK3132

最晚可采购期限
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产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
PBGA (ZEN) 196 225 mm² 15 x 15
  • Two Channel 600Mbps to 3.75Gbps Multi-Rate Transceiver
  • Supports 1X/2X Fibre Channel (FC), CPRI (x1/x2/x4), OBSAI (x1/x2/x4), and 1GbE (1000Base-X) Data Rates
  • IEEE Compliant 1000Base-X PCS Support
  • Supports Independent Channel SERDES Operation Modes in 8/10 Bit Data Modes (TBI and 8 Bit + Control)
  • Serial Side Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
  • Low Jitter LC Oscillator Jitter-Cleaner Allows use of Poor Quality REFCLK
  • Full Datapath Loopback Capability (Serial/Parallel Side)
  • Supports PRBS 27-1 and 223 – 1 Gen/Verify. Supports Standard Defined CRPAT, High and Low Frequency, and Mixed Frequency Testing.
  • GMII/RGMII: HSTL Class 1 I/O With On-Chip Termination: Programmable Input and 50 Output (1.5 and 1.8V Power Supply)
  • GMII/RGMII: Source and Data Centered I/O Timing Modes
  • Supports Jumbo Packet (9600 Byte Maximum) Operation
  • MDIO: IEEE 802.3 Clause 22 Compliant Management Data Input / Output Interface Modes (Either 1.2V or 2.5V MDIO I/O)
  • 1.2V Core, 1.5V/1.8V HSTL I/O Supply, and 2.5V LVCMOS I/O Supply
  • JTAG: IEEE 1149.1/1149.6 Test Interface
  • ±200 ppm Clock Tolerance in 1000Base-X Receive Datapaths
  • 90 nm Advanced CMOS Technology
  • Package: PBGA, 15×15mm, 196 Ball, 1mm Pitch
  • 1.1W Maximum Power Dissipation at 2CH 3.75 Gbps (1.5V HSTL Mode, Input HSTL Termination Disabled)
  • Asymmetric RX/TX Rates Supported
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
  • Two Channel 600Mbps to 3.75Gbps Multi-Rate Transceiver
  • Supports 1X/2X Fibre Channel (FC), CPRI (x1/x2/x4), OBSAI (x1/x2/x4), and 1GbE (1000Base-X) Data Rates
  • IEEE Compliant 1000Base-X PCS Support
  • Supports Independent Channel SERDES Operation Modes in 8/10 Bit Data Modes (TBI and 8 Bit + Control)
  • Serial Side Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
  • Low Jitter LC Oscillator Jitter-Cleaner Allows use of Poor Quality REFCLK
  • Full Datapath Loopback Capability (Serial/Parallel Side)
  • Supports PRBS 27-1 and 223 – 1 Gen/Verify. Supports Standard Defined CRPAT, High and Low Frequency, and Mixed Frequency Testing.
  • GMII/RGMII: HSTL Class 1 I/O With On-Chip Termination: Programmable Input and 50 Output (1.5 and 1.8V Power Supply)
  • GMII/RGMII: Source and Data Centered I/O Timing Modes
  • Supports Jumbo Packet (9600 Byte Maximum) Operation
  • MDIO: IEEE 802.3 Clause 22 Compliant Management Data Input / Output Interface Modes (Either 1.2V or 2.5V MDIO I/O)
  • 1.2V Core, 1.5V/1.8V HSTL I/O Supply, and 2.5V LVCMOS I/O Supply
  • JTAG: IEEE 1149.1/1149.6 Test Interface
  • ±200 ppm Clock Tolerance in 1000Base-X Receive Datapaths
  • 90 nm Advanced CMOS Technology
  • Package: PBGA, 15×15mm, 196 Ball, 1mm Pitch
  • 1.1W Maximum Power Dissipation at 2CH 3.75 Gbps (1.5V HSTL Mode, Input HSTL Termination Disabled)
  • Asymmetric RX/TX Rates Supported
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate

The TLK3132 is a flexible two channel independently configurable serial transceiver. It can be configured to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The TLK3132 provides high-speed bi-directional point-to-point data transmissions with up to 15 Gbps of raw data transmission capacity. The primary application of this device is in backplanes and front panel connections requiring 3.75Gbps connections over controlled impedance media of approximately 50. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.

The TLK3132 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3132 also provides 1000Base-X (PCS) layer functionality described in Clause 36 of 802.3-2002. The serial transmitter is implemented using differential Current Mode Logic (CML) with integrated termination resistors.

Many common applications may be enabled by way of externally available control pins. Detailed control of the TLK3132 on a per channel basis is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface.

The PCS (Physical Coding Sublayer) functions such as the CTC FIFO are designed to be compliant for a 1000Base-X PCS link. However, each of the PCS functions may be disabled or bypassed until the TLK3132 is operating at its most basic state, that of a simple two channel 10-bit SERDES suitable for a wide range of applications such as CPRI or OBSAI wireless infrastructure links.

The differential output swing for the TLK3132 is suitable for compliance with IEEE 802.3 Gigabit Ethernet links, which is also suitable for CPRI LV serial links. The TLK3132 provides for setting larger output signal swing suitable for CPRI HV links by setting an appropriate register bit available though MDIO.

The TLK3132 is a flexible two channel independently configurable serial transceiver. It can be configured to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The TLK3132 provides high-speed bi-directional point-to-point data transmissions with up to 15 Gbps of raw data transmission capacity. The primary application of this device is in backplanes and front panel connections requiring 3.75Gbps connections over controlled impedance media of approximately 50. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.

The TLK3132 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3132 also provides 1000Base-X (PCS) layer functionality described in Clause 36 of 802.3-2002. The serial transmitter is implemented using differential Current Mode Logic (CML) with integrated termination resistors.

Many common applications may be enabled by way of externally available control pins. Detailed control of the TLK3132 on a per channel basis is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface.

The PCS (Physical Coding Sublayer) functions such as the CTC FIFO are designed to be compliant for a 1000Base-X PCS link. However, each of the PCS functions may be disabled or bypassed until the TLK3132 is operating at its most basic state, that of a simple two channel 10-bit SERDES suitable for a wide range of applications such as CPRI or OBSAI wireless infrastructure links.

The differential output swing for the TLK3132 is suitable for compliance with IEEE 802.3 Gigabit Ethernet links, which is also suitable for CPRI LV serial links. The TLK3132 provides for setting larger output signal swing suitable for CPRI HV links by setting an appropriate register bit available though MDIO.
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类型 标题 下载最新的英语版本 日期
* 数据表 2-Channel Multi-Rate Transceiver 数据表 (Rev. A) 2009年 12月 17日
用户指南 User's Guide for Sonic MDIO Software 2013年 11月 26日
EVM 用户指南 TLK3132 2-Channel Multi-Rate Transceiver EVM User's Guide 2013年 11月 20日
白皮书 Implementing a CameraLink HS Interface Using the TLK3134 2012年 3月 30日
应用手册 高性能SERDES及其在CPRI 接口的应用分析 2010年 1月 21日
应用手册 TLK313x/CDCM7005 Multi-hop Performance 2009年 11月 1日

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仿真模型

TLK3132 IBIS Model Version 1.2

SLLM054.ZIP (307 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
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PBGA (ZEN) 196 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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