ZHCU763 March   2021

 

  1.   说明
  2.   资源
  3.   特性
  4.   应用
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Multichannel SSR with Independent Isolation Between SSR Channels
      2. 2.2.2 Design Challenge With Single Isolation
      3. 2.2.3 Multichannel SSR Drive With Single Isolation Multichannel Digital Isolator
      4. 2.2.4 Need of High-Impedance Voltage Translator
      5. 2.2.5 Design to Minimize Cross-Coupling and MOSFET Gate Pick up Due to Other SSR Switching
      6. 2.2.6 Schematic: Design of Gate-Drive Circuit
        1. 2.2.6.1 Calculation of Gate-Driver Power Consumption
      7. 2.2.7 Schematic: Digital Isolator Circuit
      8. 2.2.8 Schematic: 3.3 V to 10V_ISO, 5V_ISO Power Supply
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO7760
      2. 2.3.2 ISO7740
      3. 2.3.3 ISO7041
      4. 2.3.4 CSD19538Q2
      5. 2.3.5 CSD17382F4
      6. 2.3.6 TPL7407LA
      7. 2.3.7 TLV760
      8. 2.3.8 TLC555
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Test Equipment Needed to Validate Board
      2. 3.1.2 Test Conditions
      3. 3.1.3 Test Procedure
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Functional Tests
      2. 3.3.2 Overcurrent Testing With External Fuse
      3. 3.3.3 Surge Testing
      4. 3.3.4 Multichannel SSR Driven From Two 24-VAC Transformers
      5. 3.3.5 Alternate SSR Topology for High Voltage
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 支持资源
    4. 4.4 Trademarks
  10. 5About the Author

2.2.8 Schematic: 3.3 V to 10V_ISO, 5V_ISO Power Supply

Figure 2-12 shows the open-loop flyback power supply. Figure 2-13 shows the TIMER circuit to generate the pulse-width modulation (PWM) signal. The power supply does not have a closed loop to control the output voltage. The output voltage will be decided based on the output load. The output load will be minimum when all the SSRs are off and maximum when all the SSRs are OFF. The flyback is designed to ensure that the output voltage variation is within 7–10 V during the load change. Table 2-2 shows the design specification of the flyback power supply.

Table 2-2 Design Specification of the Flyback Power Supply
Parameter Minimum Typical Maximum Comments
Flyback Input Voltage3.2 V3.3 V3.4 VAssuming 2% tolerance
Output Voltage6.5 V8.5 V10 V
Output Current5.5 mA10.2 mA15 mATyp value when half of the SSR are ON

The flyback transformer used in the reference design board is the coupled inductor 744889030330 (Wurth). The coupled inductor has a turns ratio of 1:3 and primary inductance of 33 µH. The PWM frequency used is 250 kHz with a 34% duty cycle. An alternate part for the flyback transformer could be LPR4012-223DMR (Coil Craft) having 1:3 turns ratio and 22-µH primary inductance. With the couple inductor LPR4012-223DMR, the frequency used should be around 400 kHz. MOSFET Q1 is a logic FET to enable switching with a 3.3-V supply. The selected coupled inductor should provide sufficient function isolation voltage for the 24-VAC supply operation.

The TLC555 timer is configured to create a PWM frequency of 250 kHz at a 34% duty cycle. The designer can also generate a PWM from the MCU and connect to pin 9 of connector J3. If the PWM from the timer is used, then populate R15 and do not populate R26. If PWM from the MCU is used, then populate R26 and do not populate R15. The diodes D7 and D6 in the TIMER circuit are used to generate PWM frequency less than 50%. The resistors R16, R17, and capacitor C14 are tuned to get the desired frequency and duty cycle. See the TLC555 LinCMOS™ Timer Data Sheet for detailed design. The PWM from the timer or MCU is connected to the input of the buffer U6 (SN74LV1T34DCKR) and the gate resistor used is 100 Ω. Make sure that the resistor R12 is not populated. The MOSFET Q1 can be driven directly from the MCU as well (with a minimum 4- to 6-mA drive capacity from the MCU), and in that case remove U6 and populate R12 with a 0-Ω resistor. The gate resistance R7 should be increased to limit the MCU pin current.

The linear regulator TLV76050 generates 5V_ISO from the 10V_ISO. The 5V_ISO is used as secondary side supply for ISO7760 and ISO7740 digital isolators. The 10V_ISO (In schematic Figure 2-12, the 10V_ISO node is marked as 12V_ISO) is used as the power supply for the gate-driver circuit of SSR MOSFET (by connecting R8 and removing R9). The secondary side of the digital isolator can be powered with 3.3 V as well and in that case a 3.3-V output regulator can be used. The TLV70433 is a recommended 3.3-V regulator option in case an ultra-low quiescent current is required.

The resistor R5 is used at the output of the flyback to ensure the minimum load to ensure no load voltage regulation within control. The Zener diode D2 is used as a voltage clamp for overvoltage protection. IN1 – IN10 are the relay on and relay off control signal from the MCU for the SSR channels 1 to 10, in order. The VGD_ISO is the supply to the gate-drive PNP transistor. The VGD_ISO is connected to the 10-V supply by populating R8. The resistor R9 is not populated. The reference design uses 3.3-V voltage at the input of the isolated power supply by keeping R2 populated and R4 not populated.

GUID-20210223-CA0I-DWBR-L1NK-2PM29BLPPVH9-low.gif Figure 2-12 Open-Loop Flyback Power Supply
GUID-20210223-CA0I-TQTM-QPJJ-9GVKSWQ6FTRD-low.gif Figure 2-13 TIMER to Generate PWM Signal and Interface Connector