ZHCSNG6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

General Considerations

Designing for high power density requires consideration of noise coupling and thermal management. A four-layer PCB structure is highly recommended to use inner layers to help reduce current-loop areas and provide heat-spreading for surface-mount semiconductors.

  • Provide internal-layer copper areas to improve heat dissipation of high-power SMDs, particularly for switching MOSFETs and power diodes. Use multiple thermal-vias to conduct heat from outer pads to inner-layers and supporting copper areas.
  • To avoid capacitive noise coupling, do not cross outer-layer signals over copper areas that carry high-frequency switching voltage.
  • To avoid inductive noise coupling, keep switching current loops as small as possible, and do not run signal tracks in parallel with such loops.
  • Arrange the conducted-EMI filter components such that they do not allow switching noise to bypass them and affect the input. Avoid running switching signals through the EMI filter area.
  • Use multiple vias to connect high-current tracks and planes between layers.

Figure 10-1 summarizes the critical layout guidelines, and more detail is further elaborated in the descriptions below.

Figure 10-1 Typical Schematic with Layout Considerations