ZHCSNG6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

Brown-In and Brown-Out

The VS pin senses the negative voltage level of the auxiliary winding during the on-time of the primary-side switch (QL) to detect an under-voltage condition of the input DC or AC line. When the bulk voltage (VBULK) is too low, UCC28781-Q1 stops switching and no VO restart attempt is made until the input line voltage is back into normal range. As QL turns on with PWML, the negative voltage level of the auxiliary winding voltage (VAUX) is equal to VBULK divided by primary-to-auxiliary turns ratio (NPA) of the transformer, which is NP / NA. During this time, the voltage on VS pin is clamped to about 250 mV below AGND. As a result, VAUX can create a line-sensing current (IVSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (RVS1). With IVSL proportional to VBULK, it can be used to compare against two under-voltage thresholds, IVSL(RUN) and IVSL(STOP).

The following discussion, equations, and figures involving brown-in and brown-out thresholds are based on AC-line input conditions, but are generally applicable to DC input voltages as well. For an application using a DC input, substitute VDC(BI) for VAC(BI), VDC(BO) for VAC(BO) and remove the √2 factor from each equation and figure in this section.

The target brown-in AC voltage (VAC(BI)) can be programmed by the proper selection of RVS1. For every UVLO cycle of VDD, there are at least four initial test pulses from PWML to check IVSLcondition. IVSL of the first test pulse is ignored. If IVSL ≤ IVSL(RUN) is valid for the next three consecutive test pulses, the controller stops switching, the RUN pin goes low, and a new UVLO start cycle is initiated after VVDD reaches VVDD(OFF). On the other hand, if IVSL > IVSL(RUN) occurs, VO soft start sequence is initiated.

Equation 14. GUID-5C2AF1E2-BFC4-4BE9-A140-E08A6BFEF58D-low.gif

The brown-out AC voltage (VAC(BO)) is set internally by approximately 83% of VAC(BI), which provides enough hysteresis to compensate for possible sensing errors through the auxiliary winding.

Equation 15. GUID-DCD55743-1DC9-449E-92CD-FEF77051B243-low.gif

A 60-ms timer (tBO) is used to bypass the effect of line ripple content on the IVSL sensing. Only when the IVSL ≤ IVSL(STOP) condition lasts longer than 60 ms (i.e. typically three line cycles of 50 Hz) and 3 additional switching cycles verify the condition, the brown-out fault is triggered. If switching is interrupted, the brown-out fault will remain pending without shut-down until the 3 verification cycles complete. The fault is reset after VVDD reaches VVDD(OFF). Figure 7-37 shows an example of the timing sequence of brown-out and brown-in protections for the case of an actual input brown-out condition. An application with DC input that has considerable ripple on the bulk voltage will behave similar to the AC-line bulk-ripple case.

GUID-0D777FB1-8767-46BD-8CD1-BEA9553D1061-low.gifFigure 7-37 Timing Diagram of Brown-Out/Brown-In Response on AC Line Events

The tBO timer is started at the moment IVSL ≤ IVSL(STOP) is detected during the PWML on-time. The timer is cleared when IVSL > IVSL(STOP) is detected. In the case of an overshoot voltage on the output, switching will stop until the output voltage recovers to the regulation level. If the tBO timer is triggered by IVSL ≤ IVSL(STOP) while in the valley of the bulk ripple voltage, and then switching is stopped the status of IVSL cannot be detected and updated. The timer cannot be cleared without switching to sample IVSL, and the 60-ms timer may elapse even though no brown-out condition exists. To prevent an unwarranted shut-down, the 3 additional switching cycles sample the condition once switching does resume, to verify or dismiss the pending apparent brown-out fault. An extended output overshoot condition longer than tBO can result from a sudden load drop combined with a drop in the regulation reference due to reduction of cable compensation. Figure 7-38 shows an example of the timing sequence for the case of an apparent brown-out cancelled by 3 verifying pulses.

GUID-A237C859-983C-4FB5-A93B-7CDF04F91563-low.gifFigure 7-38 Timing Diagram of Brown-Out Response on Extended Output Overshoot.