ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fS(ref) Setting | ADC Dual-Rate Control | DAC Dual-Rate Control | DAC Data Path Control | 0 | 0 | 0 | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | fS(ref) Setting | R/W | 0h | This bit controls the fS(ref) setting. This register setting controls timers related to the AGC time constants. 0: fS(ref) = 48 kHz 1: fS(ref) = 44.1 kHz |
6 | ADC Dual-Rate Control | R/W | 0h | 0: ADC dual-rate mode is disabled 1: ADC dual-rate mode is enabled The ADC dual-rate mode must match the DAC dual-rate mode. |
5 | DAC Dual-Rate Control | R/W | 0h | 0: DAC dual-rate mode is disabled 1: DAC dual-rate mode is enabled |
4:3 | DAC Data Path Control | R/W | 0h | 00: DAC data path is off (muted) 01: DAC data path plays left-channel input data 10: DAC data path plays right-channel input data 11: DAC data path plays mono mix of left- and right-channel input data |
2:0 | Reserved | R/W | 0h | Reserved. Always write zeros to these bits. |