ZHCSEG5E October   2015  – September 2017 TMDS171

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working (Retimer Mode Only)
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
      4. 8.4.4 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1  Local I2C Overview
        1. 8.5.1.1 BIT Access Tag Conventions
      2. 8.5.2  CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)
      3. 8.5.3  CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)
      4. 8.5.4  CSR BIT Field Definitions - Misc Control (offset: 00001001) (reset: 02h)
      5. 8.5.5  CSR BIT Field Definitions - Misc Control (offset: 00001010) (reset: B1h)
      6. 8.5.6  CSR BIT Field Definitions - Misc Control (offset: 00001011) (reset: 00h)
      7. 8.5.7  CSR BIT Field Definitions - Misc Control (offset: 00001100) (reset: 00h)
      8. 8.5.8  CSR BIT Field Definitions - Equalization Control Register (offset: 00001101) (reset: 01h)
      9. 8.5.9  CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)
      10. 8.5.10 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)
      11. 8.5.11 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)
      12. 8.5.12 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)
      13. 8.5.13 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)
      14. 8.5.14 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)
      15. 8.5.15 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)
      16. 8.5.16 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)
      17. 8.5.17 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)
      18. 8.5.18 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)
      19. 8.5.19 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)
      20. 8.5.20 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)
      21. 8.5.21 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)
      22. 8.5.22 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)
      23. 8.5.23 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)
      24. 8.5.24 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)
      25. 8.5.25 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)
      26. 8.5.26 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)
      27. 8.5.27 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Chain Showing DDC Connections
      2. 9.1.2 DDC Pull Up Resistors
    2. 9.2 Source Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Sink Side Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关文档 
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

Detailed Description

Overview

The TMDS171 is a digital video interface (DVI) or high-definition multimedia interface (HDMI) retimer. The TMDS171 supports four TMDS channels, Audio Return Channel (SPDIF_IN/ARC_OUT), Hot Plug Detect, and a Digital Display Control (DDC) interfaces. The TMDS171 supports signaling rates up to 3.4 Gbps to allow for the highest resolutions of 4k2k30p 24 bits per pixel and up to WUXGA 12-bit color depth or 1080p with higher refresh rates. The TMDS171 can automatically configure itself as a re-driver at low data rate (< 1 Gbps) or as a re-timer above this data rate. For passing compliance and reducing system level design issues several features have been included such as TMDS output amplitude adjust using an external resistor on the VSADJ pin and source termination selection control. Device operation and configuration can be programmed by pin strapping or I2C. Four TMDS171s can be used on one I2C bus when I2C_EN enable and device address set by A0/A1.

To reduce active power the TMDS171 supports dual power supply rails of 1.2 V on VDD and 3.3 V on VCC. The TMDS171 supports several methods of power management. It can enter power down mode using three methods; (1) HPD is low; (2) Writing an 1 to register 09h[3]; or (3) de-asserting OE. If using OE, the device must be reprogrammed via I2C if it was originally programmed this way. The SIG_EN pin enables the signal detect circuit that provides an automatic power-management feature during normal operation. When no valid signal is present on the inputs the device enters Stand by mode. By disabling the detect circuit the receiver block is always on. DDC bridge supports 100 Kbps data rate default and 400 kbps adjustable by software.

TMDS171 supports both fixed EQ gain control or adaptive equalization to compensate for different lengths of input cables or board traces. The EQ gain can be software adjusted by I2C control or selection between two fixed values or adaptive equalization by pin strapping EQ_SEL pin. Implementers can use the TX_TERM_CTL pin to change the transmitter termination impedance for better output performance when working in HDMI1.4b or leave it floating. When floating the TMDS171 in conjunction with the rate detect will automatically change its output termination to be compatible with HDMI1.4b requirements.

The TMDS171 supports single ended mode audio return channel. To assist in ease of implementation the TMDS171 supports receive lane swapping and receive polarity swap. When swapping the input lanes IN_CLK and IN_D2 swap and IN_D1 and IN_D0 swap with each other. Swap works in both retimer and redriver mode. Polarity swap will swap the receive pins n and p channel polarity in each lane and is only available during retimer mode. Both lane swap and polarity swap can be implemented at the same time in retimer mode using I2C control.

Two versions of the device are offered to support extended commercial temperature range 0ºC to 85ºC (TMDS171) or industrial operational temperature range from -40ºC to 85ºC (TMDS171I).

Functional Block Diagram

TMDS171 TMDS171I fbd_sllen7.gif

Feature Description

Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It is critical to transition the OE from a low level to high after the VCC supply has reached the minimum recommended operating voltage. This is achieved by a control signal to the OE input, or by an external capacitor connected between OE and GND. To insure the TMDS171 is properly reset, the OE pin must be de-asserted for at least 100 μs before being asserted. When OE is re-asserted the TMDS171 will have to be reprogrammed if it was programmed by I2C and not pin strapping. When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor. Refer to the latest reference schematic for TMDS171; consider approximately 200 nF capacitor as a reasonable first estimate for the size of the external capacitor. Both OE implementations are shown in Figure 21 and Figure 22.

TMDS171 TMDS171I external_capacitor_controlled_OE_sllsen7.gif Figure 21. External Capacitor Controlled OE
TMDS171 TMDS171I OE_input_active_controller_sllsen7.gif Figure 22. OE Input from Active controller

Operation Timing

TMDS171 starts to operate after the OE signal is properly set after power up timing complete. See Figure 23, Figure 24, Table 1. If OE is held low until VDD and VCC become stable there is no rail sequence requirement.

TMDS171 TMDS171I Power_up_Timing_sllsen7.gif Figure 23. Power up Timing for TMDS171
TMDS171 TMDS171I CDR_Timing_sllsen7.gif Figure 24. CDR Timing for TMDS171

Table 1. Power Up and Operation Timing Requirements

DESCRIPTION MIN TYP MAX UNIT
td1 VDD Stable before VCC 0 200 µs
td2 VDD and VCC stable before OE de-assertion 100 µs
td3 CDR active operation after retimer mode initiated 15 ms
td4 CDR turn off time after retimer mode de-assert 120 ns
VDD(ramp) VDD supply ramp up requirements 100 ms
VCC(ramp) VCC supply ramp up requirements 100 ms

Swap and Polarity Working (Retimer Mode Only)

TMDS171 incorporates swap function which can set the input lanes in swap mode. The IN_D2 will route to the OUT_CLK position by swapping with IN_CLK. The IN_D1 swaps with IN_D0. The Swap function only changes the input pins. The EQ setup follows the new mapping, see Figure 25. This function can be used with the SWAP/POL pin 1 and control the register 0x09h bit 7 for SWAP enable. The Swap function works in both redriver and retimer mode. The TMDS171 can also swap the input polarity signals. When SWAP/POL is high the n and p pins on each lane will swap. Polarity swap only works when in retimer mode. When this function is enabled and the device is in automatic cross over mode between redriver and retimer modes, care must be taken to avoid losing polarity swap. When the data rate drops to the redriver level, the polarity swap is lost.

Table 2. SWAP Pin Mapping

Normal Op SWAP = L or CSR 0x09h bit 7 is 1'b1
IN_D2 → OUT_D2 IN_D2 → OUT_CLK
IN_D1 → OUT_D1 IN_D1 → OUT_D0
IN_D0 → OUT_D0 IN_D0 → OUT_D1
IN_CLK → OUT_CLK IN_CLK → OUT_D2
TMDS171 TMDS171I Swap_Function_sllsen7.gif Figure 25. TMDS171 Swap Function

TMDS Inputs

Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input data channel contains an adaptive or fixed equalizer to compensate for Inter-Symbol Interference (ISI) due to cable, connector, and/or board trace losses. The voltage at the TMDS input pins must be limited under the absolute maximum ratings. TMDS input pins have incorporated failsafe circuits. An unused input channel can be externally biased to prevent output oscillation by connecting the N input pin to be grounded through a 1-kΩ resistor and the other pin left open. The input pins can be polarity changed through local I2C register when in retimer mode.

TMDS Inputs Debug Tools

There are two methods for debugging a system to make sure the inputs to the TMDS171 are valid. A TMDS error checker is implemented to provide a rough Bit Error Rate per data lane. This allows the system implementer to determine how the link between the source and TMDS171 is performing on all three data lanes. See CSR BIT FIELD DEFINITIONS – RX PATTERN VERIFIER CONTROL/STATUS register.

If a high error count is evident the TMDS171 has a way to view the general receiver eye quality. A tool is available that uses the I2C link to down load the data that can be plotted for an eye diagram. This is available per data lane. This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal on the data pins. A clock at the proper frequency is required on the IN_CLK pins to generated the expected output data rate.

Receiver Equalizer

The equalizer used to clean up inter-symbol interference (ISI) jitter/loss from the bandwidth-limited board traces or cables. TMDS171 supports fixed receiver equalizer and adaptive equalizer by setting the EQ_SEL/A0 pin or through I2C. When EQ_SEL/A0 is high, the EQ gain is fixed to 10 dB and when set low the EQ gain is set to 7.5 dB. TMDS171 operates in adaptive equalizer mode when EQ_SEL/A0 pin is left floating. The EQ gain will be automatically adjusted based on the data rate to compensate for trace or cable loss. Implementers can enable the various EQ settings through local I2C control.

TMDS171 TMDS171I gr_EQ_LLSEJ2.gif
Figure 26. Adaptive EQ Gain Curve

Input Signal Detect Block

When SIG_EN is enabled, the TMDS looks for a valid TMDS clock signal input. The terminations on the TMDS data lines are connected and the device is fully functional when a valid signal is detected. If no valid TMDS clock signal is detected, the device enters standby mode waiting for a valid signal at the clock input. The internal CDR is shut down and all of the TMDS outputs are in high-Z status. TMDS signal detect circuit can be set as enable by SIG_EN pin or through local I2C control but is default disabled. Designers are recommended to activate this function in normal operation for power saving.

Audio Return Channel

The Audio Return Channel in TMDS171 enables a TV, via a single HDMI cable, to send audio data “upstream” to an A/V receiver or surround audio controller, increasing user flexibility and eliminating the need for any separate S/PDIF audio connection. The TMDS171 supports single mode audio return channel. Implementers can send the S/PDIF signal to SPDIF_IN. The signal from ARC_OUT is sent to HDMI connectors and is passed through the general HDMI cable to audio receiver. By I2C control, customer can disable ARC_OUT by register. Enabled by default after initialization.

Transmitter Impedance Control

Source termination is disabled at data rates < 2 Gbps. When the data rate is between 2 Gbps and 3.4 Gbps, the output signal may be better if the termination value around 150 Ω to 300 Ω depending upon system implementation. TMDS171 supports two different source termination impedances for ease of implementation. Pin 36, TX_TERM_CTL, offers a selection option to choose the output termination impedance value.

Table 3. TX Termination Control

Control Pin 36 DESCRIPTION
TX_TERM_CTL = H The transmit Termination is disabled
TX_TERM_CTL = L Reserved
TX_TERM_CTL = Z Automatic select the impedance
  • 2 Gbps > DR < 3.4 Gbps – 150 - 300 Ω differential near end termination
  • DR < 2 Gbps – no termination

TMDS Outputs

A 1% precision resistor, 7.06 kΩ, connected from VSADJ to ground is recommended to allow the differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.

TMDS171 TMDS171I Driver_Termination_Circuit_sllsen7.gif Figure 27. TMDS Driver and Termination Circuit

In Figure 27, if VCC (TMDS171 supply) and AVCC (sink termination supply) are both powered, the TMDS output signals are high impedance when OE = high. Both supplies being active are the normal operating condition. Again refer to Figure 27, if VCC is on and AVCC is off, the TMDS outputs source a typical 5 mA current through each termination resistor to ground. A total of 33 mW of power is consumed by the terminations independent of the OEB logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the power source of the device is off and the power source to termination is on, the IO(off), output leakage current, specification ensures the leakage current is limited to 45 μA or less. The PRE_SEL pin provides – 2 dB de-emphasis gain, allowing output signal pre-conditioning to offset interconnect losses from the TMDS171 outputs to a TMDS receiver. De-emphasis is recommended to be set at 0 dB while connecting to a receiver through short PCB route. The VOD of the data lanes and clock lane can be adjusted through I2C. See Table 11 for detail. Figure 1 shows the different output voltages based on the different VSADJ settings.

Pre-Emphasis/De-Emphasis

The TMDS171 provides de-emphasis as a way to compensate for ISI loss between the TMDS171 outputs and a TMDS receiver. There are two methods to implement this function. When in pin strapping mode the PRE_SEL pin controls this function. The PRE_SEL pin provides - 2 dB or 0 dB de-emphasis, which allows the output signal pre-conditioning. De-emphasis is recommended to be set at 0-dB while connecting to a receiver through short PCB traces. When pulled to ground through a 65 kΩ resistor - 2 dB can be realized, see Figure 9. When using I2C, reg0Ch[1:0] is used to make these adjustments.

As there are times that true pre-emphasis may be the best solution there are two methods to accomplish this. If pin strapping is being used the best method is to reduce the VSADJ resistor value thus increasing the VOD swing and then pulling the PRE_SEL pin to ground using a 65 kΩ resistor, see Figure 28. If using I2C there are two methods to accomplish this. The first is similar to pin strapping but reducing VSADJ resistor value and then implementing - 2 db de-emphasis through I2C, reg0Ch[1:0] = 01. The second method is to increase the VOD swing by setting reg0Ch[7:5] = 011 and reg0Ch[1:0] = 01 which will accomplish the same pre-emphasis value, see Figure 29. Note: De-emphasis is only implement able during retimer mode. In redriver mode this function is not available.

TMDS171 TMDS171I pre-emphasis_pin_strap_sllsen7.gif Figure 28. Pre-emphasis Using Pin Strapping
TMDS171 TMDS171I pre-emphasis_I2C_sllsen7.gif Figure 29. Pre-emphasis Using I2C

Device Functional Modes

Retimer Mode

Clock and Data Recovery Circuits (CDR) are used to track, sample and retime the equalized data bit streams. The CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz, is transferred to the TMDS outputs. Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock above approximately 100 MHz when jitter cleaning is needed for robust operation. The retimer operates at about 100 Mhz – 340 MHz pixel clock (1 – 3.4 Gbps). At pixel clock below about 100 MHz, the TMDS171 automatically bypasses the internal retimer, and operates as a redriver. When the video source changes resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire lock to the new data bit streams. During the clock frequency detection period and the retimer acquisition period that last approximately 7 ms, the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver. The TMDS171 can support retimer mode across the full data rate range of 250 Mbps - 3.4 Gbps by setting DEV_FUNC_MODE bits at reg0Ah[1:0], See Table 9. For compliance testing such as JTOL for 480 Mbps the PLL must be forced to lock.

Redriver Mode

The TMDS171 can function as a redriver which compensates for ISI channel loss. In this mode, power is reduced as the CDR and PLL are turned off. When in automatic mode, the TMDS171 is in redriver mode for data rates < 1.0 Gbps. By using I2C the device can be put in Redriver mode for the complete data range of 250 Mbps to 3.4 Gbps. This is done by writing a 00 to register 0Ah[1:0]. If the link has excessive random jitter then retimer mode is the best operating mode. If the link has excessive random jitter, the retimer mode is the best operating mode. When in redriver mode, the device compensates for ISI loss only. When in redriver mode compliance is not ensured as skew compensation and retiming functions are disabled. If a significant amount of random jitter is present, the system may not pass compliance at the connector.

DDC Functional Description

The TMDS171 solves sink/source level issues by implementing a master/salve control mode for the DDC bus. When the TMDS171 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it transfers the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback from the downstream device, the TMDS171 pulls up or pulls down the SDA_SRC bus and delivers the signal to the source.

The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct value to address 0Bh through the I2C interface. The DDC lines are 5 V tolerant when the device is powered off. The HPD goes to high impedance when VCC is under low power conditions < 1.5 V.

NOTE

The TMDS171 utilizes clock stretching for DDC transactions. As there are sources and sinks that do not perform this function correctly as system may not work correctly as DDC transactions are incorrectly transmitted/recieved. To overcome this a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL sink. The TMDS171 will need its SDA_SNK and SCL_SNK pins connected to this link.

Mode Selection Functional Description

Mode Selection Definition: reg0Ah[7] is the mode select register, see Table 9. This bit lets the receiver know where the device is located in a system for the purpose of centering the AEQ point. The TMDS171 is targeting sink or dock applications so the default value is 1 which centers the EQ at 12 dB to 13 dB, see Table 12. If the TMDS171 is in a source application the value should be changed to a 0 which centers the EQ at 6.5 dB to 7.5 dB.

Register Maps

Local I2C Overview

The TMDS171 local I2C interface is enabled when I2C_EN/PIN is high. The SCL_CTL and SDA_CTL terminals are used for I2C clock and I2C data respectively. The TMDS171 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for TMDS171 decides by the combination of EQ_SEL/A0 and A1. Table 4 clarifies the TMDS171 target address.

Table 4. TMDS171 I2C Device Address Description

TMDS171 I2C Device Address
A1/A0 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (W/R) HEX
00 1 0 1 1 1 1 0 0/1 BC/BD
01 1 0 1 1 1 0 1 0/1 BA/BB
10 1 0 1 1 1 0 0 0/1 B8/B9
11 1 0 1 1 0 1 1 0/1 B6/B7

The typical source application of the TMDS171 is as a retimer in a TV connecting the HDMI input connector and an internal HDMI receiver through flat cables. The register setup can adjust by source side. When TMDS171 used in sink side application, it received data from input connector and transmit to receiver. The local I2C is not 5 V tolerant and only support 3.3 V. Local I2C buses run at 400 kHz supporting fast-mode I2C operation.

The following procedure is followed to write to the TMDS171 I2C registers:

  1. The master initiates a write operation by generating a start condition (S), followed by the TMDS171 7-bit address and a zero-value “W/R” bit to indicate a write cycle
  2. The TMDS171 acknowledges the address cycle
  3. The master presents the sub-address (I2C register within TMDS171) to be written, consisting of one byte of data, MSB-first
  4. The TMDS171 acknowledges the sub-address cycle
  5. The master presents the first byte of data to be written to the I2C register
  6. The TMDS171 acknowledges the sub-address cycle
  7. TMDS171 acknowledges the byte transfer
  8. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TMDS171
  9. The master terminates the write operation by generating a stop condition (P)

The following procedure is followed to read the TMDS171 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the TMDS171 7-bit address and a one-value “W/R” bit to indicate a read cycle
  2. The TMDS171 acknowledges the address cycle
  3. The TMDS171 transmit the contents of the memory registers MSB-first starting at register 00h.
  4. The TMDS171 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer
  5. If an ACK is received, the TMDS171 transmits the next byte of data
  6. The master terminates the read operation by generating a stop condition (P)

NOTE

Nno sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation.

Refer to Table 4 for TMDS171 local I2C register descriptions. Reads from reserved fields not described return zeros, and writes are ignored.

BIT Access Tag Conventions

A table of bit descriptions is typically included for each register description that indicates the bit field name, field description, and the field access tags. The field access tags are described in Table 5.

Table 5. Access Tags

ACCESS TAG NAME DESCRIPTION
R Read The field shall be read by software
W Write The field shall be written by software
S Set The field shall be set by a write of one. Writes of Zero to the field have no effect
C Clear The field shall be cleared by a write of one. Writes of Zero to the field have no effect
u Update Hardware may autonomously update this field
NA No Access Not accessible or not applicable

CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)

Figure 30. CSR Bit Field Definitions, DEVICE_ID (00h ≈ 07h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 6. CSR Bit Field Definitions, DEVICE_ID (00h ≈ 07h)

Bit Field Type Reset Description
7:0 DEVICE_ID R 00h ≈ 07h

These fields return a string of ASCII characters “TMDS171” preceded by one space characters.


TMDS171:
0x00 – 0x07 = {- 0x54”T”, 0x4D”M”, 0x44”D”, 0x53”S”, 0x31”1”, 0x37”7”, 0x31”1”, 0x20},

CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)

Figure 31. CSR Bit Field Definitions, REV _ID (08h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 7. CSR Bit Field Definitions, REV _ID (08h)

Bit Field Type Reset Description
7:0 REV _ID R 01h This field identifies the device revision.
0000001– TMDS171 Revision 1

CSR BIT Field Definitions – Misc Control (offset: 00001001) (reset: 02h)

Figure 32. CSR Bit Field Definitions – Misc Control (09h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
R/W/U R/W/U R R/W/U R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 8. CSR Bit Field Definitions – Misc Control (09h)

Bit Field Type Reset Description
7 Lane_SWAP R/W/U 1’b0 This field Swaps the input lanes as per Figure 25.
0 --- Disable (default) No Lane Swap
1 --- enable: Swaps input lanes (Redriver and Retimer Mode)
Note: field is loaded from SWAP/POL pin; Writes are ignored when I2C_EN/PIN = 0
6 LANE_POLARITY R/W/U 1’b0 Swaps the input Data and Clock lanes polarity.
0 – Disabled: No polarity swap
1 – Swaps the input Data and Clock lane polarity (Retimer Mode Only)
Note: field is loaded from SWAP/POL pin; Writes are ignored when I2C_EN/PIN = 0
5 Reserved R 1’b0 Reserved
4 SIG_EN R/W/U 1’b0 This field enable the clock lane activity detect circuitry.
0 – Disable(Default) Clock detector circuit closed and receiver always works in normal operation.
1 – Enable , Clock detector circuit will make receiver automatic enter the standby state when no valid data detect.
Note: field is loaded from SIG_EN pin; Writes are ignored when I2C_EN/PIN = 0
3 PD_EN R/W 1’b0 0 – Normal working (default)
1 – Forced Power down by I2C, Lowest Power state
2 HPD_AUTO_PWRDWN_DISABLE R/W 1’b0 0 – Automatically enters power down mode based on HPD_SNK (default)
1 – Will not automatically enter power down mode
1:0 I2C_DR_CTL R/W 2’b10 I2C data rate supported for configuring device.
00 – 5 Kbps
01 – 10 Kbps
10 – 100 Kbps(default)
11 – 400 Kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling 400 Kbps mode)

CSR BIT Field Definitions – Misc Control (offset: 00001010) (reset: B1h)

Figure 33. CSR Bit Field Definitions – Misc Control (0Ah)
7 6 5 4 3 2 1 0
1 0 1 1 0 0 0 1
R/W R/W R/W R/W R W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 9. CSR Bit Field Definitions – Misc Control (0Ah)

Bit Field Type Reset Description
7 Application Mode Selection R/W 1’b1 See Mode Selection
TMDS171
0 – Source
1 – Sink (Default)
6 HPDSNK_GATE_EN R/W 1’b0 Swaps the input Data and Clock lanes polarity. The field set the HPD_SNK signal pass through to HPD_SRC or not and HPD_SRC whether held in the de-asserted state.
0 – HPD_SNK passed through to the HPD_SRC ( default )
1 – HPD_SNK will not pass through to the HPD_SRC.
5 EQ_ADA_EN R/W 1’b1 This field enable the equalizer functioning state; Writes are ignored when I2C_EN/PIN = 0
0 – Fixed EQ
1 – Adaptive EQ (default)
4 EQ_EN R/W 1’b1 This field enable the Equalizer; Writes are ignored when I2C_EN/PIN = 0
0 -- EQ disable
1 – EQ enable (default)
3 Reserved R 1’b0 Reserved
2 APPLY_RXTX_CHANGES W 1’b0 Self-clearing write-only bit.
Writing a 1 to this bit will apply new TX_TERM, HDMI_TWPST1, EQ_EN, EQ_ADA_EN, VSWING, Fixed EQ value settings to the clock and data lanes. Writes to the respective registers do not take immediate effect.
This bit does not need to be written if I2C configuration occurs while OE or HPD_SNK are low, I2C PD_EN=1 or there is no HDMI clock applied and SIG_EN is high.
1:0 DEV_FUNC_MODE. R/W 2’b01 This field selects the Device Working Function Mode.
00 – Redriver Mode across full range 250 Mbps – 3.4 Gbps
01 - Automatic Redriver to Retimer Cross Over at 1.0 Gbps (default)
10 - Reserved
11 - Retimer Mode across full range 250 Mbps – 3.4 Gbps
When changing crossover point, need to toggle PD_EN or toggle external HPD_SNK.

CSR BIT Field Definitions – Misc Control (offset: 00001011) (reset: 00h)

Figure 34. CSR Bit Field Definitions – Misc Control (0Bh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R/W/U R/W/U R/W R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 10. CSR Bit Field Definitions – Misc Control (0Bh)

Bit Field Type Reset Description
7:5 Reserved R 2’b000 Reserved
4:3 TX_TERM_CTL RWU 2’b00 Controls termination for HDMI TX; Writes are ignored when I2C_EN/PIN = 0
00 – No termination
01 – 150 to 300 Ω
10 – Reserved.
11 – Reserved
2 DDC_DR_SEL R/W 1’b0 Defines the DDC output speed for both DDC bridge and AUX-DDC Bridge.
0 = 100 kbps (default)
1 = 400 kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling 400 Kbps mode)
1:0 Reserved R 2’b00 Reserved

CSR BIT Field Definitions – Misc Control (offset: 00001100) (reset: 00h)

Figure 35. CSR Bit Field Definitions – Misc Control (0Ch)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W/U R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 11. CSR Bit Field Definitions – Misc Control (0Ch)

Bit Field Type Reset Description
7:5 VSWING_DATA R/W 3’b000 Data Output Swing Control (Need Design input on what is available)
000 – Vsadj set (default)
001 – Increase by 7%
010 – Increase by 13%
011 – Increase by 18%
100 – Decrease by 30%
101 – Decrease by 22%
110 – Decrease by 15%
111 – Decrease by 7%
4:2 VSWING_CLK R/W 13’b000 Clock Output Swing Control: Default is set by DR which means standard based swing values but this allows for the swing to be overridden by selecting one of the following values.
000 – Set by Data Rate
001 – Increase by 7%
010 – Increase by 13%
011 – Increase by 18%
100 – Decrease by 30%
101 – Decrease by 22%
110 – Decrease by 15%
111 – Decrease by 7%
1:0 HDMI_TWPST1[1:0] R/W/U 2’b00 HDMI pre-emphasis FIR post-cursor-1 signed tap weight.
00 – No pre-emphasis
01 – 2 dB pre-emphasis.
10 – Reserved
11 – Reserved
Note: Reflects value of PRE_SEL pin; Writes are ignored when I2C_EN/PIN = 0

CSR BIT Field Definitions – Equalization Control Register (offset: 00001101) (reset: 01h)

Figure 36. CSR BIT Field Definitions – Equalization Control Register (0Dh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
R R R/W R/W R/W R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 12. CSR BIT Field Definitions – Equalization Control Register (0Dh)

Bit Field Type Reset Description
7:6 Reserved R 2’b00 Reserved
5:3 Data Lane EQ R/W 1’b000 Sets Fixed EQ Values
000 – 0 dB
001 – 4.5 dB
010 – 6.5 dB
011 – 8.5 dB
100 – 10.5 dB
101 – 12 dB
110 – 14 dB
111 – 16.5 dB
2:1 Clock Lane EQ R/W 13’b000 - Sets Fixed EQ Values.
00 – 0 dB
01 – 1.5 dB
10 – 3 dB
011 – RSVD
0 Reserved R 1’b1 Reserved

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)

Figure 37. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 13. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh)

Bit Field Type Reset Description
7:4 PV_SYNC[3:0] R/W 4’b0000 Pattern timing pulse. This field is updated for 8UI once every cycle of the PRBS generator. 1 bit per lane.
3:0 PV_LD[3:0] R/W 4’b0000 Load pattern-verifier controls into RX lanes. When asserted high, the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are enabled into the corresponding RX lane. These values are then latched and held when PV_LD[n] is subsequently de-asserted low. 1 bit per lane.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)

Figure 38. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/U R/U R/U R/U R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 14. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh)

Bit Field Type Reset Description
7:4 PV_SYNC[3:0] R/U 4’b0000 Pattern verification mismatch detected. 1 bit per lane.
3:0 PV_LD[3:0] R/U 4’b0000 Pattern search/training in progress. 1 bit per lane.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)

Figure 39. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 15. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h)

Bit Field Type Reset Description
7 PV_CP20 R/W 1’b0 Customer pattern length 20/16 bits.
0 – 16 bits
1 – 20 bits
6 Reserved R 1’b0 Reserved
5:3 PV_LEN[2:0] R,W 3’b000 ]PRBS pattern length
000 – PRBS7
001 – PRBS11
010 – PRBS23
011 – PRBS31
100 – PRBS15
101 – PRBS15
110 – PRBS20
111 – PRBS20
2:0 PV_SEL[24:0] R/W 3’b000 Pattern select control
000 – Disabled
001 – PRBS
010 - Clock
011 - Custom
1xx – Timing only mode with sync pulse spacing defined by PV_LEN

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)

Figure 40. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 16. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h)

Bit Field Type Reset Description
7 PV_CP[7:0] R/W ‘h00 Custom pattern data.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)

Figure 41. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 17. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h)

Bit Field Type Reset Description
7 PV_CP[15:8] R/W ‘h00 Custom pattern data.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)

Figure 42. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (13h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 18. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (13h)

Bit Field Type Reset Description
7:4 Reserved R 4’b0000 Reserved
3:0 PV_CP[19:16] R/W 4’b0000 Custom pattern data. Used when PV_CP20 = 1’b1.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)

Figure 43. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (14h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 19. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (14h)

Bit Field Type Reset Description
7:3 Reserved R 5’b00000 Reserved
2:0 PV_THR[2:0] R/W 3’b000 Pattern-verifier retain threshold.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)

Figure 44. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (15h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R/S/U R/S/U R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 20. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (15h)

Bit Field Type Reset Description
7 DESKEW_CMPLT R 1’b0 Indicates that TMDS lane deskew has completed when high.
6:5 Reserved R 2’b00 Reserved
4 BERT_CLR R/S/U 1’b0 Clear BERT counter (on rising edge).
3 TST_INTQ_CLR R/S/U 1’b0 Clear latched interrupt flag.
2:0 TST_SEL[2:0] R/W 3’b000 Test interrupt source select.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)

Figure 45. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 21. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h)

Bit Field Type Reset Description
7:4 PV_DP_EN[3:0] R/W 4’b0000 Enable datapath verified based on DP_TST_SEL, 1 bit per lane
3 Reserved R 1’b0 Reserved
2:0 DP_TST_SEL[2:0] R/W 3’b000 Selects pattern reported by BERT_CNT[11:0],
TST_INT[0] and TST_INTQ[0] and PV_DP_EN is non-zero.
000 – TMDS disparity or data errors
001 – FIFO errors
010 – FIFO overflow errors
011 – FIFO underflow errors
100 – TMDS deskew status
101,110,111 – Reserved.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)

Figure 46. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/U R/U R/U R/U R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 22. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h)

Bit Field Type Reset Description
7:4 TST_INTQ[3:0] R/U 4’b0000 Latched interrupt flag. 1 bit per lane
3:0 RTST_INT[3:0] R/U 4’b0000 Test interrupt flag. 1 bit per lane.

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)

Figure 47. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/U R/U R/U R/U R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 23. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h)

Bit Field Type Reset Description
7:0 BERT_CNT[7:0] R/U ‘h00 BERT error count. Lane 0

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)

Figure 48. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 24. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h)

Bit Field Type Reset Description
7:4 Reserved R 4’b0000 Reserved
3:0 BERT_CNT[11:8] R/U 4’b0000 BERT error count. Lane 0

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)

Figure 49. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/U R/U R/U R/U R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 25. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah)

Bit Field Type Reset Description
7:0 BERT_CNT[19:12]. R/U ‘h00 BERT error count. Lane 1

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)

Figure 50. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 26. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh)

Bit Field Type Reset Description
7:4 Reserved R 4’b0000 Reserved
3:0 BERT_CNT[23:20] R/U 4’b0000 BERT error count. Lane 1

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)

Figure 51. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/U R/U R/U R/U R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 27. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch)

Bit Field Type Reset Description
7:0 BERT_CNT[31:24] R/U ‘h00 BERT error count. Lane 2

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)

Figure 52. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 28. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh)

Bit Field Type Reset Description
7:4 Reserved R 4’b0000 Reserved
3:0 BERT_CNT[35:32] R/U 4’b0000 BERT error count. Lane 2

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)

Figure 53. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/U R/U R/U R/U R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 29. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh)

Bit Field Type Reset Description
7:0 BERT_CNT[19:12] R/U ’h00 BERT error count. Lane 3

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)

Figure 54. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R R R/U R/U R/U R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 30. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh)

Bit Field Type Reset Description
7:4 Reserved R 4’b0000 Reserved
3:0 BERT_CNT[23:20] R/U 4’b0000 BERT error count. Lane 3

CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)

Figure 55. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R/W R/W R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 31. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h)

Bit Field Type Reset Description
7 PWR_DWN_STATUS R 1’b0 Power Down Status Bit.
0 = Normal Operation (default)
1 = Device in Power Down Mode
6 STB_STATUS R 1’b0 Standby Status Bit
0 = Normal Operation (default)
1 = Device in Standby Mode
5:0 Reserved R 6’b000000 Reserved