ZHCSDC6D November 2014 – February 2018 AMC7836
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR-B7 | CLR-B6 | CLR-B5 | CLR-B4 | CLR-A3 | CLR-A2 | CLR-A1 | CLR-A0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLR-B7 | R/W | 0 |
This register uses software to force the DAC into a clear state.
If CLRn = 1, DAC_n is forced into a clear state. If CLRn = 0, DAC_n is restored to normal operation. |
6 | CLR-B6 | R/W | 0 | |
5 | CLR-B5 | R/W | 0 | |
4 | CLR-B4 | R/W | 0 | |
3 | CLR-A3 | R/W | 0 | |
2 | CLR-A2 | R/W | 0 | |
1 | CLR-A1 | R/W | 0 | |
0 | CLR-A0 | R/W | 0 |