ZHCSAL0D March   2016  – August 2020 TPD3S716-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1.     18
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  AEC-Q100 Qualified
      2. 8.3.2  Short-to-Battery and Short-to-Ground Protection on VBUS_CON
      3. 8.3.3  Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
      4. 8.3.4  ESD Protection on VBUS_CON, VD+, VD–
      5. 8.3.5  Low RON nFET VBUS Switch
      6. 8.3.6  High Speed Data Switches
      7. 8.3.7  Adjustable Hiccup Current Limit up to 2.4-A
      8. 8.3.8  Fast Over-Voltage Response Time
      9. 8.3.9  Independent VBUS and Data Enable Pins for Configuring both Host and Client/OTG Mode
      10. 8.3.10 Fault Output Signal
      11. 8.3.11 Thermal Shutdown Feature
      12. 8.3.12 16-Pin SSOP Package
      13. 8.3.13 Reverse Current Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Overvoltage Condition
      3. 8.4.3 Overcurrent Condition
      4. 8.4.4 Short-Circuit Condition
      5. 8.4.5 Device Logic Table
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Short-to-Battery Tolerance
        2. 9.2.2.2 Maximum Current on VBUS
        3. 9.2.2.3 Power Dissipation and Junction Temperature
        4. 9.2.2.4 USB Data Rate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VBUS Path
    2. 10.2 VIN Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Layout Optimized for Thermal Performance
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from Revision C (June 2016) to Revision D (August 2020)

  • 向 Section 1 部分添加了功能安全链接Go
  • 更新了整个文档中的表格、图和交叉参考的编号格式Go

Changes from Revision B (April 2016) to Revision C (June 2016)

  • 将 Section 1 部分中的可调节断续电流限制 从 1.7A 更改为 2.4AGo
  • 更新了 Section 3 部分Go
  • Changed Current through VBUS switch from 1.7 A to 2.4 AGo
  • Updated the RADJ minimum resistance to 57 kΩ in Section 6.5 tableGo
  • aDDED new current limit values to Section 6.7 table Go
  • Updated Figure 8-1 Go
  • Updated IVBUS Operating Maximum in Figure 9-7 to go up to 2.4 AGo

Changes from Revision A (April 2016) to Revision B (April 2016)

Changes from Revision * (March 2016) to Revision A (April 2016)

  • 将器件状态从产品预发布 更改为量产数据 Go