SNVU775 April   2021 LP8732-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2OTP Memory Device Settings
  4. 3Power-up and Power Down Sequence
  5. 4Register Bits Loaded From OTP Memory

3 Power-up and Power Down Sequence

This section shows the power-up and power-down sequence for the device. The power-up and power-down delays for each rail are shown in Figure 3-1.

GUID-20210331-CA0I-T9FG-VFBC-257FDF0HPJKC-low.svg Figure 3-1 LP873244-Q1Power-up and Power Down Sequence