SLVUC20A March   2021  – August 2022 LP876242-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Getting Started
    1. 2.1 The GUI Tool
  5. 3EVM Details
    1. 3.1 Terminal Blocks
    2. 3.2 Test Point Descriptions
    3. 3.3 Configuration Headers
    4. 3.4 Connectors
    5. 3.5 DIP Switches
    6. 3.6 EVM Control and GPIO
  6. 4Customization
    1. 4.1 Changing the Communication Interface
  7. 5Schematic, Layout, and Bill of Materials
  8. 6Additional Resources
  9. 7Revision History

3.5 DIP Switches

There are three DIP switches S1, S2 and S3 on the back side of the PCB. S1 switch can be used for configuring chip select for target device in multi PMIC/stacked use case. S2 and S3 switches allow the user to disconnect the level shifter from the PMIC GPIOs or serial interfaces. The level shifter has pull-ups on the MCU side that can cause unwanted high state on the GPIO signals if configured in high impedance state. See the Table 3-7 for the descriptions of the switches.

Table 3-7 DIP Switches
SwitchPinSignal line
S11-12CS5
2-11CS4
3-10CS3
4-9CS2
5-8CS1
6-7GPIO2
S21-16SDA_I2C1/SDI_SPI
2-15SCL_I2C1/SCK_SPI
3-14SDA_I2C2/SDO_SPI
4-13SCL_I2C2/CS_SPI
5-12GPIO1
6-11GPIO2
7-10GPIO3
8-9 GPIO4
S31-16GPIO5
2-15 GPIO6
3-14 GPIO7
4-13 GPIO8
5-12 GPIO9
6-11 GPIO10
7-10 Not connected
8-9 nINT