SLVUBG8A July   2018  – December 2020 TPS23755

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Electrical Specifications
  4. 3Description
  5. 4Schematic
  6. 5General Configuration and Description
    1. 5.1 Physical Access
  7. 6TPS23755EVM-894 Performance Data
    1. 6.1 Startup to PSE and DCDC Startup
    2. 6.2 Transient Response
    3. 6.3 Efficiency
    4. 6.4 Load Regulation
    5. 6.5 Recovery from VOUT Short
    6. 6.6 Slew Rate Adjust
  8. 7EVM Assembly Drawings and Layout Guidelines
    1. 7.1 PCB Drawings
    2. 7.2 Layout Guidelines
    3. 7.3 EMI Containment
  9. 8Bill of Materials
  10.   Revision History

7.2 Layout Guidelines

The layout of the PoE frontend should follow power and EMI or ESD best-practice guidelines. A basic set of recommendations includes:

  • Pin 22 of the TPS23755 is omitted from the IC to ensure high voltage clearance from Pin 24 (DRAIN). Therefore, the Pin 22 footprint should be removed when laying out the TPS23755.
  • It is recommended having at least 8 vias (VSS) connecting the exposed thermal pad through a top layer plane (2 oz copper recommended) to a bottom VSS plane (2 oz copper recommended) to help with thermal dissipation.
  • The Pin 24 of the TPS23755 should be near the power transformer and the current sense resistor should be close to Pin 1 of the TPS23755 to minimize the primary loop.
  • Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode bridges, TVS and 0.1-μF capacitor, and TPS23755 converter input bulk capacitor.
  • Make all leads as short as possible with wide power traces and paired signal and return.
  • No crossovers of signals from one part of the flow to another are allowed.
  • Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output.
  • Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay copper fills in the power path.

The DC-to-DC converter layout benefits from basic rules such as:

  • Having at least 4 vias (VDD) near the power transformer pin connected to VDD through multiple layer planes to help with thermal dissipation of the power transformer.
  • Having at least 6 vias (secondary ground) near the power transformer pin connected to secondary ground through multiple layer planes to help with thermal dissipation of the power transformer.
  • Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses, which include the power semiconductors and magnetics.
  • Minimize the trace length of high current power semiconductors and magnetic components.
  • Use the ground plane for the switching currents carefully.
  • Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside the power supply.
  • Proper spacing around the high-voltage sections of the converter.