The board layout for the TPS54429EEVM-608 and is shown in Figure 6-1 through Figure 6-6. The top layer contains the main power traces for VIN, VO, and ground. Also on the top layer are connections for the pins of the TPS54429E and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitor are located as close to the integrated circuit as possible. The input and output connectors, test points, and most of the components are located on the top side. R4, the power-good pullup, is located on the back side. Analog ground and power ground are connected at a single point on the top layer near pin 5 of the TPS54429E. The internal layer 1 is a split plane containing analog and power grounds. The internal layer 2 is primarily power ground. Also, a fill area of VIN and a trace routing VIN enables the control jumper JP1. The bottom layer is primarily analog ground. Traces also connect VIN, the power-good signal, and a feedback trace from VOUT connects to the voltage setpoint divider network.

Figure 6-1 Top Assembly

Figure 6-2 Top Layer

Figure 6-3 Internal Layer 1

Figure 6-4 Internal Layer 2

Figure 6-5 Bottom Layer as Seen From Back Side

Figure 6-6 Bottom Assembly as Seen From Back Side