SLVAEV2 June   2020 DRV8873-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 DRV8873H-Q1 (HW variant)
    2. 4.2 DRV8873S-Q1 (SPI variant)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the DRV8873-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2 for HW variant, see Table 4-6 for SPI variant)
  • Pin open-circuited (see Table 4-3 for HW variant, see Table 4-7 for SPI variant)
  • Pin short-circuited to an adjacent pin (see Table 4-4 for HW variant, see Table 4-8 for SPI variant)
  • Pin short-circuited to supply (see Table 4-5 for HW variant, see Table 4-9 for SPI variant)

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance