SLOS739A July   2012  – March 2016

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - I/O Pin Characteristics
    6. 7.6  Master Clock Characteristics
    7. 7.7  Speaker Amplifier Characteristics
    8. 7.8  Headphone Amplifier and Line Driver Characteristics
    9. 7.9  Protection Characteristics
    10. 7.10 I2C Serial Control Port Requirements and Specifications
    11. 7.11 Serial Audio Port Timing
    12. 7.12 Typical Characteristics
      1. 7.12.1 Headphone Typical Characteristics
      2. 7.12.2 Line Driver Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Supply
      2. 9.3.2  I2C Address Selection and Fault Output
      3. 9.3.3  Device Protection System
        1. 9.3.3.1 Overcurrent (OC) Protection With Current Limiting
        2. 9.3.3.2 Overtemperature Protection
        3. 9.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      4. 9.3.4  Clock, Auto Detection, and PLL
      5. 9.3.5  PWM Section
      6. 9.3.6  SSTIMER Functionality
      7. 9.3.7  2.1-Mode Support
        1. 9.3.7.1 Supply Pumping and Polarity Inversion for 2.1 Mode
      8. 9.3.8  PBTL-Mode Support
      9. 9.3.9  I2C Serial Control Interface
        1. 9.3.9.1 Single- and Multiple-Byte Transfers
        2. 9.3.9.2 Single-Byte Write
        3. 9.3.9.3 Multiple-Byte Write
        4. 9.3.9.4 Single-Byte Read
        5. 9.3.9.5 Multiple-Byte Read
      10. 9.3.10 Dynamic Range Control (DRC)
      11. 9.3.11 Bank Switching
      12. 9.3.12 Serial Data Interface
        1. 9.3.12.1 Serial Interface Control and Timing
          1. 9.3.12.1.1 I2S Timing
          2. 9.3.12.1.2 Left-Justified
          3. 9.3.12.1.3 Right-Justified
      13. 9.3.13 DirectPath Headphone/Line Driver
        1. 9.3.13.1 Using Headphone Amplifier in TAS5721
        2. 9.3.13.2 Using Line Driver Amplifier in TAS5721
    4. 9.4 Device Functional Modes
      1. 9.4.1 Output Mode and MUX Selection
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
        1. 9.5.1.1 I2C Device Address Change Procedure
      2. 9.5.2 26-Bit 3.23 Number Format
    6. 9.6 Register Maps
      1. 9.6.1  Clock Control Register (0x00)
      2. 9.6.2  Device ID Register (0x01)
      3. 9.6.3  Error Status Register (0x02)
      4. 9.6.4  System Control Register 1 (0x03)
      5. 9.6.5  Serial Data Interface Register (0x04)
      6. 9.6.6  System Control Register 2 (0x05)
      7. 9.6.7  Soft Mute Register (0x06)
      8. 9.6.8  Volume Registers (0x07, 0x08, 0x09, 0x0A)
      9. 9.6.9  Volume Configuration Register (0x0E)
      10. 9.6.10 Modulation Limit Register (0x10)
      11. 9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
      12. 9.6.12 Pwm Shutdown Group Register (0x19)
      13. 9.6.13 Start/stop Period Register (0x1A)
      14. 9.6.14 Oscillator Trim Register (0x1B)
      15. 9.6.15 BKND_ERR Register (0x1C)
      16. 9.6.16 Input Multiplexer Register (0x20)
      17. 9.6.17 Channel 4 Source Select Register (0x21)
      18. 9.6.18 PWM Output MUX Register (0x25)
      19. 9.6.19 DRC Control (0x46)
      20. 9.6.20 Bank Switch and EQ Control (0x50)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Component Selection and Hardware Connections
        2. 10.2.2.2 I2C Pullup Resistors
        3. 10.2.2.3 Digital I/O Connectivity
        4. 10.2.2.4 Recommended Startup and Shutdown Procedures
          1. 10.2.2.4.1 Recommended Use Model
            1. 10.2.2.4.1.1 Initialization Sequence
            2. 10.2.2.4.1.2 Normal Operation
            3. 10.2.2.4.1.3 Shutdown Sequence
            4. 10.2.2.4.1.4 Power-Down Sequence
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 DVDD and AVDD Supplies
    2. 11.2 PVDD Power Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9 Detailed Description

9.1 Overview

The TAS5721 device is an efficient stereo I2S input Class-D audio power amplifier with a digital audio processor and a DirectPath headphone/line driver.

The digital audio processor of the device uses noise shaping and customized correction algorithms to achieve a great power efficiency and high audio performance. Also, the device has up to eight Equalizers per channel and two -band configurable Dynamic Range Control (DRC).

The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of the device enables its use in a multitude of applications.

The device has an integrated DirectPath headphone amplifier / line driver to increase system level integration and reduce total solution costs. DirectPath architecture eliminates the requirement for external dc-blocking output capacitors.

The TAS5721 device is a slave-only device that is controlled by a bidirectional I2C interface that supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control interface is used to program the registers of the device and read the device status. The PWM of this device operates with a carrier frequency between 384 kHz and 354 kHz, depending the sampling rate. This device allows the use of the same clock signal for both MCLK and BCLK (64xFs) when using a sampling frequency of 44.1 kHz or 48 kHz.

This device can be used in three different modes of operation, Stereo BTL Mode, Single Filter PBTL Mono Mode, and 2.1 Mode.

9.2 Functional Block Diagram

TAS5721 TAS5721_PLAIN.gif Figure 48. Functional Block Diagram
TAS5721 dap_process_structure_slos739.gif Figure 49. DAP Process Structure

9.3 Feature Description

9.3.1 Power Supply

To facilitate system design, the TAS5721 needs only a 3.3-V supply in addition to the PVDD power-stage supply. The required sequencing of the power supplies is shown in the Recommended Use Model section. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BSTRPx) and power-stage supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. As shown in the Typical Application section, it is recommended to use ceramic capacitors, for the bootstrap supply pins. These capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD pin is decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in the Typical Application section.

The TAS5721 is fully protected against erroneous power-stage turn-on due to parasitic gate charging.

9.3.2 I2C Address Selection and Fault Output

ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the Typical Application section in order to set the I2C address. Pulling this pin HIGH through the resistor results in setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the address to 0011010 (0x34).

During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to it's default state when register 0x02 is cleared. The device will pull the fault pin low for over-current, over-temperature, over-voltage lock-out, and under-voltage lock-out.

9.3.3 Device Protection System

9.3.3.1 Overcurrent (OC) Protection With Current Limiting

The device has independent, fast reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by a protection system. If the high-current condition situation persists, a protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. After the power stage enters into this state, the power stage will attempt to restart after a period of time defined in register 0x1C. If the high-current condition persists, the device will begin the shutdown and retry sequence again. The device will return to normal operation once the fault condition is removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down.

9.3.3.2 Overtemperature Protection

The TAS5721 has an overtemperature-protection system. If the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being asserted low. The TAS5721 recovers automatically once the temperature drops approximately 30 °C.

9.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5721 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 4.1 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or on either PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being asserted low.

9.3.4 Clock, Auto Detection, and PLL

The TAS5721 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control Register section.

The TAS5721 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 × fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock control register.

TAS5721 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute) and then force PLL to operate in a reduced capacity using the internal oscillator as a reference clock. Once the clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process, the default volume will be restored in a single step (also called hard unmute) by default. If desired, the unmuting process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E).

9.3.5 PWM Section

The TAS5721 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs up to three PWM audio output channels.

The PWM modulation block has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. It is important to note that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.

9.3.6 SSTIMER Functionality

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin capacitance. The SSTIMER capacitor size determines the start-up time, 2200 pF is the maximum recommended value. The SSTIMER pin can be left floating when using BD modulation, but leaving the capacitor connected does not represent any issue.

9.3.7 2.1-Mode Support

The TAS5721 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation. To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must be set to 1. The SSTIMER pin should be left floating in this mode.

9.3.7.1 Supply Pumping and Polarity Inversion for 2.1 Mode

The high degree of correlation between the left and right channels of a stereo audio signal dictates that, when the left audio signal is positive, the right audio signal tends to be positive as well. When the Class D is configured for single-ended operation (as would be the case for Single Device 2.1 Operation), this results in both outputs drawing current from the supply rail "in phase". Similarly, when the left audio signal is negative, the right audio signal tends to be negative as well. For single-ended operation, both outputs will likewise force current into the ground rail. This can lead to a phenomenon called "supply pumping" in which the capacitances on the PVDD rail begin to store charge- raising the voltage level of PVDD as well. This noise injection onto the rail is in phase with and at a similar frequency of the signal being produced by the amplifier output stage. This phenomenon can cause issues for other devices attached to the PVDD rail. The problem does not occur for BTL outputs since outputs of both polarities are always present for each channel. To combat supply pumping in 2.1 Mode, the device has an integrated speaker-mode volume negation feature, which, essentially introduces a polarity inversion (shift by 180°) to any of the given channels. By setting the correct bit in 0x20[31:24], it is possible to invert the polarity of the DAP channels that drive the PWM modulator blocks. This allows, for instance, the left channel to operate with its default polarity, while the right channel could have its polarity inverted to balance current flow into and out of the supplies. This procedure could have an adverse implication on the stereo imaging of the audio system because, if the speakers in the system are connected in the same manner as they would be connected when being driven by traditional BTL channels, the phase of the signals being sent to the speakers is 180° out of phase. In order to prevent this from occurring, the speaker on the negated channel must be connected "backwards" (i.e. the Class D signal for the negated channel gets connected to the negative speaker terminal and the positive terminal is grounded). In this way, supply pumping is reduced while keeping the effective signal polarity the same. The table above includes register settings which enable the polarity inversion, so care should be taken to adjust the polarity of the speakers if this feature is left enabled. Of course this feature can be left disabled if desired, provided the supply pumping phenomenon doesn't cause any other system level issues

9.3.8 PBTL-Mode Support

The TAS5721 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected after the LC filter. In order to put the part in PBTL configuration, the PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value of 0x3A.

9.3.9 I2C Serial Control Interface

The TAS5721 DAP has a bidirectional inter-integrated circuit (I2C) interface that is compatible with the I2C bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation (400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.

9.3.9.1 Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses 0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. For example, if a write command is received for a biquad subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded.

Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5721 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5721. For I2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data is discarded.

9.3.9.2 Single-Byte Write

As shown in Figure 50, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5721 internal memory address being accessed. After receiving the address byte, the TAS5721 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5721 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer.

TAS5721 t0036-01.gif Figure 50. Single-Byte Write Transfer

9.3.9.3 Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 51. After receiving each data byte, the TAS5721 responds with an acknowledge bit.

TAS5721 t0036-02.gif Figure 51. Multiple-Byte Write Transfer

9.3.9.4 Single-Byte Read

As shown in Figure 52, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5721 address and the read/write bit, TAS5721 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5721 address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5721 again responds with an acknowledge bit. Next, the TAS5721 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.

TAS5721 t0036-03.gif Figure 52. Single-Byte Read Transfer

9.3.9.5 Multiple-Byte Read

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5721 to the master device as shown in Figure 53. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

TAS5721 t0036-04.gif Figure 53. Multiple Byte Read Transfer

9.3.10 Dynamic Range Control (DRC)

The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subchannel.

The DRC input/output diagram is shown in Figure 54.

Refer to GDE software tool for more description on T, K, and O parameters.

TAS5721 m0091-02_los556.gif
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
 • Each DRC has adjustable threshold, offset, and compression levels.
 • Programmable energy, attack, and decay time constants
 • Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
    and decay times can be set slow enough to avoid pumping.
Figure 54. Dynamic Range Control
TAS5721 b0265-01_los549.gif
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 55. DRC Structure

9.3.11 Bank Switching

The TAS5721 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32-kHz mode, bank 2 is used in 44.1- or 48-kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5721 to detect automatically a change in the input sample rate and switch to the appropriate bank without any MCU intervention.

An external controller configures bankable locations (0x29-0x36, 0x3A-0x3F, and 0x58-0x5F) for all three banks during the initialization sequence.

If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5721 automatically swaps the coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate change.

By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5721 automatically swaps banks based on the sample rate.

Command sequences for updating DAP coefficients can be summarized as follows:

  1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not influenced by subsequent sample rate changes.
    OR
  2. Bank switching enabled:
    1. Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients.
    2. Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients.
    3. Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients.
    4. Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50.

9.3.12 Serial Data Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5721 DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

9.3.12.1 Serial Interface Control and Timing

The I2S mode is set by writing to register 0x04.

9.3.12.1.1 I2S Timing

I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions.

TAS5721 t0034-01.gif

NOTE:

All data presented in 2s-complement form with MSB first.
Figure 56. I2S 64-fS Format
TAS5721 t0092-01.gif

NOTE:

All data presented in 2s-complement form with MSB first.
Figure 57. I2S 48-fS Format
TAS5721 t0266-01_los549.gif

NOTE:

All data presented in 2s-complement form with MSB first.
Figure 58. I2S 32-fS Format

9.3.12.1.2 Left-Justified

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.

TAS5721 t0034-02.gif

NOTE:

All data presented in 2s-complement form with MSB first.
Figure 59. Left-Justified 64-fS Format
TAS5721 t0092-02.gif

NOTE:

All data presented in 2s-complement form with MSB first.
Figure 60. Left-Justified 48-fS Format
TAS5721 t0266-02_los549.gif

NOTE:

All data presented in 2s-complement form with MSB first.
Figure 61. Left-Justified 32-fS Format

9.3.12.1.3 Right-Justified

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions.

TAS5721 t0034-03.gif Figure 62. Right Justified 64-fS Format
TAS5721 t0092-03.gif Figure 63. Right Justified 48-fS Format
TAS5721 t0266-03_los549.gif Figure 64. Right Justified 32-fS Format

9.3.13 DirectPath Headphone/Line Driver

The TAS5721 device has a stereo output which can be used as a line driver or a headphone driver that can output 2-Vrms stereo. An audio system can be set up for different applications using this device.

9.3.13.1 Using Headphone Amplifier in TAS5721

The device can be represented as shown in Figure 65: analog inputs (single-ended) as DR_INA (pin 7) and DR_INB (pin 10) with the outputs DR_OUTA (pin 8) and DR_OUTB (pin 9).

TAS5721 S0490-02_SLOS739.gif Figure 65. Headphone/Line Driver with Analog Input

DR_SD pin can be used to turn ON or OFF the headphone amplifier and line driver.

Speaker channels are independent of headphone and line driver in this mode.

9.3.13.2 Using Line Driver Amplifier in TAS5721

Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 66 illustrates the conventional line driver amplifier connection to the load and output signal.

DC blocking capacitors for headphone amps are often large in value, and a mute circuit is needed during power up to minimize click and pop for both headphone and line driver. The output capacitors and mute circuits consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal.

TAS5721 line_driver_los739.gif Figure 66. Conventional and DirectPath HP and Line Driver

The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail.

Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode.

The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail, combining this with the built in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors.

The bottom block diagram and waveform of Figure 66 illustrate the ground-referenced headphone and line driver architecture. This is the architecture of the TAS5721.

9.4 Device Functional Modes

9.4.1 Output Mode and MUX Selection

The TAS5721 is a highly configurable device, capable of operating in 2.0, Single Device 2.1 and parallel bridge tied load (PBTL) configurations. Addtionally, the modulation scheme can be changed for the channels to operate either in AD or BD Modulation mode. While many configurations are possible because of this flexibility, the majority of use cases uses will operate in one of the configurations shown below. For ease of use and reduced complexity, the figure below outlines both the register settings and the output configurations required to set the device up for operation in these various modes.

The output configuration quick reference table below highlights the controls that are required to configure the device for various operational modes. Please note that other controls, which are not directly related to the output configuration muxes may also be required. For example, the Inter Channel Delay (ICD) settings will likely need to be modified to optimize for idle channel noise, cross-talk, and distortion performance for each of these considerations, in addition to start and stop time and others. Please consult the respective registers for these controls to optimize for various other performance parameters and use cases.

Table 1. Output Configuration Quick Reference

OUTPUT CONFIGURATION MODULATION MODE REGISTER SETTINGS BLOCK DIAGRAM
2.0 (Stereo BTL) AD for Both Outputs 0x20[23] = 0
0x20[19] = 0
0x20[15:8] = 0x77
0x05[7] = 0
0x05[2] = 0
0x25[23:8] = 0x0213
0x1A[7:0] = 0x0F
TAS5721 B0487-01_SLOS739.gif
BD for Both Outputs 0x20[23] = 1
0x20[19] = 1
0x20[15:8] = 0x77
0x05[7] = 0
0x05[2] = 0
0x25[23:8] = 0x0213
0x1A[7:0] = 0x0A
TAS5721 B0487-02_SLOS739.gif
Single Device 2.1 (Stereo Single Ended + Mono BTL)


Note: In these described configurations, the polarity of the signal being sent to SPK_OUTB is inverted. For this reason, care should be taken to ensure that the speakers are connected as shown in the block diagram.
AD for Both SE Outputs
AD for Single BTL Output
0x20[23] = 0
0x20[19] = 0
0x20[3] = 0
0x05[7] = 1
0x05[2] = 1
0x25[23:8] = 0x0132
0x1A[7:0] = 0x95
0x20[7:4] = 0x7
0x21[8] = 0
0x20[25] = 1
TAS5721 B0487-03_SLOS739.gif
AD for both SE Outputs
BD for Single BTL Output
0x20[23] = 0
0x20[19] = 0
0x20[3] = 1
0x05[7] = 1
0x05[2] = 1
0x25[23:8] = 0x0132
0x1A[7:0] = 0x95
0x20[7:4] = 0x7
0x21[8] = 0
0x20[25] = 1
TAS5721 B0487-04_SLOS739.gif
1.0 Mono PBTL AD 0x05[7] = 0
0x05[5] = 0
0x05[2] = 0
0x19[7:0] = 0x3A
0x1A[7:0] = 0x0F
0x20[23] = 0
0x20[15:12] = 0x7
0x25[23:8] = 0x0123
TAS5721 B0488-02_SLOS739.gif
BD 0x05[7] = 0
0x05[5] = 0
0x05[2] = 0
0x19[7:0] = 0x3A
0x1A[7:0] = 0x0A
0x20[23] = 1
0x20[15:12] = 0x7
0x25[23:8] = 0x0123
TAS5721 B0488-01_SLOS739.gif

9.5 Programming

9.5.1 General I2C Operation

The I2C bus employs two signals to communicate between integrated circuits in a system: (data) SDA and (clock) SCL. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 67. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5721 holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

TAS5721 t0035-01.gif Figure 67. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 67.

Pin ADR/FAULT defines the I2C device address. An external 15-kΩ pull down on this pin gives a device address of 0x34 and a 15-kΩ pull up gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010 (0x34).

9.5.1.1 I2C Device Address Change Procedure

  • Write to device address change enable register, 0xF8 with a value of 0xF9 A5 A5 A5.
  • Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.
  • Any writes after that should use the new device address XX.

9.5.2 26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 68.

TAS5721 m0125-01_los599.gif Figure 68. 3.23 Format

The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 68. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 69 applied to obtain the magnitude of the negative number.

TAS5721 m0126-01_los599.gif Figure 69. Conversion Weighting Factors—3.23 Format to Floating Point

Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 70.

TAS5721 m0127-01_los599.gif Figure 70. Alignment of 3.23 Coefficient in 32-Bit I2C Word

Table 2. Sample Calculation for 3.23 Format

dB LINEAR DECIMAL HEX (3.23 FORMAT)
0 1 8,388,608 0080 0000
5 1.7782794 14,917,288 00E3 9EA8
–5 0.5623413 4,717,260 0047 FACC
X L = 10(X/20) D = 8,388,608 × L H = dec2hex (D, 8)

Table 3. Sample Calculation for 9.17 Format

dB LINEAR DECIMAL HEX (9.17 FORMAT)
0 1 131,072 2 0000
5 1.77 231,997 3 8A3D
–5 0.56 73,400 1 1EB8
X L = 10(X/20) D = 131,072 × L H = dec2hex (D, 8)

9.6 Register Maps

Table 4. Serial Control Interface Register Summary

SUBADDRESS REGISTER NAME NO. OF BYTES CONTENTS DEFAULT
VALUE
A u indicates unused bits.
0x00 Clock control register 1 Description shown in subsequent section 0x6C
0x01 Device ID register 1 Description shown in subsequent section 0x00
0x02 Error status register 1 Description shown in subsequent section 0x00
0x03 System control register 1 1 Description shown in subsequent section 0xA0
0x04 Serial data interface register 1 Description shown in subsequent section 0x05
0x05 System control register 2 1 Description shown in subsequent section 0x40
0x06 Soft mute register 1 Description shown in subsequent section 0x00
0x07 Master volume 1 Description shown in subsequent section 0xFF (mute)
0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0A Channel 3 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0B–0x0D 1 Reserved(1)
0x0E Volume configuration register 1 Description shown in subsequent section 0x91
0x0F 1 Reserved(1)
0x10 Modulation limit register 1 Description shown in subsequent section 0x02
0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC
0x12 IC delay channel 2 1 Description shown in subsequent section 0x54
0x13 IC delay channel 3 1 Description shown in subsequent section 0xAC
0x14 IC delay channel 4 1 Description shown in subsequent section 0x54
0x15–0x18 1 Reserved(1)
0x19 PWM channel shutdown group register 1 Description shown in subsequent section 0x30
0x1A Start/stop period register 1 Description shown in subsequent section 0x0F
0x1B Oscillator trim register 1 Description shown in subsequent section 0x82
0x1C BKND_ERR register 1 Description shown in subsequent section 0x02
0x1D–0x1F 1 Reserved(1)
0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772
0x21 Ch 4 source select register 4 Description shown in subsequent section 0x0000 4303
0x22–0x24 4 Reserved(1)
0x25 PWM MUX register 4 Description shown in subsequent section 0x0102 1345
0x26–0x28 4 Reserved(1)
0x29 ch1_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2A ch1_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2B ch1_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2C ch1_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2D ch1_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2E ch1_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2F ch1_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x30 ch2_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x31 ch2_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x32 ch2_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x33 ch2_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x34 ch2_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x35 ch2_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x36 ch2_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x37–0x39 4 Reserved(1)
0x3A DRC1 ae(2) 8 u[31:26], ae[25:0] 0x0080 0000
DRC1 (1 – ae) u[31:26], (1 – ae)[25:0] 0x0000 0000
0x3B DRC1 aa 8 u[31:26], aa[25:0] 0x0080 0000
DRC1 (1 – aa) u[31:26], (1 – aa)[25:0] 0x0000 0000
0x3C DRC1 ad 8 u[31:26], ad[25:0] 0x0080 0000
DRC1 (1 – ad) u[31:26], (1 – ad)[25:0] 0x0000 0000
0x3D DRC2 ae 8 u[31:26], ae[25:0] 0x0080 0000
DRC 2 (1 – ae) u[31:26], (1 – ae)[25:0] 0x0000 0000
0x3E DRC2 aa 8 u[31:26], aa[25:0] 0x0080 0000
DRC2 (1 – aa) u[31:26], (1 – aa)[25:0] 0x0000 0000
0x3F DRC2 ad 8 u[31:26], ad[25:0] 0x0080 0000
DRC2 (1 – ad) u[31:26], (1 – ad)[25:0] 0x0000 0000
0x40 DRC1-T 4 T1[31:0] (9.23 format) 0xFDA2 1490
0x41 DRC1-K 4 u[31:26], K1[25:0] 0x0384 2109
0x42 DRC1-O 4 u[31:26], O1[25:0] 0x0008 4210
0x43 DRC2-T 4 T2[31:0] (9.23 format) 0xFDA2 1490
0x44 DRC2-K 4 u[31:26], K2[25:0] 0x0384 2109
0x45 DRC2-O 4 u[31:26], O2[25:0] 0x0008 4210
0x46 DRC control 4 Description shown in subsequent section 0x0000 0000
0x47–0x4F 4 Reserved(1)
0x50 Bank switch control 4 Description shown in subsequent section 0x0F70 8000
0x51 Ch 1 output mixer 12 Ch 1 output mix1[2] 0x0080 0000 
Ch 1 output mix1[1] 0x0000 0000
Ch 1 output mix1[0] 0x0000 0000
0x52 Ch 2 output mixer 12 Ch 2 output mix2[2] 0x0080 0000 
Ch 2 output mix2[1] 0x0000 0000 
Ch 2 output mix2[0] 0x0000 0000 
0x53 Ch 1 input mixer 16 Ch 1 input mixer[3] 0x0080 0000 
Ch 1 input mixer[2] 0x0000 0000
Ch 1 input mixer[1] 0x0000 0000
Ch 1 input mixer[0] 0x0080 0000 
0x54 Ch 2 input mixer 16 Ch 2 input mixer[3] 0x0080 0000 
Ch 2 input mixer[2] 0x0000 0000
Ch 2 input mixer[1] 0x0000 0000
Ch 2 input mixer[0] 0x0080 0000 
0x55 Channel 3 input mixer 12 Channel 3 input mixer [2] 0x0080 0000
Channel 3 input mixer [1] 0x0000 0000
Channel 3 input mixer [0] 0x0000 0000
0x56 Output post-scale 4 u[31:26], post[25:0] 0x0080 0000
0x57 Output pre-scale 4 u[31:26], pre[25:0] (9.17 format) 0x0002 0000
0x58 ch1 BQ[7] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x59 ch1 BQ[8] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x5A Subchannel BQ[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x5B Subchannel BQ[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x5C ch2 BQ[7] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x5D ch2 BQ[8] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x5E pseudo_ch2 BQ[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x5F 4 Reserved(1)
0x60 Channel 4 (subchannel) output mixer 8 Ch 4 output mixer[1] 0x0000 0000
Ch 4 output mixer[0] 0x0080 0000
0x61 Channel 4 (subchannel) input mixer 8 Ch 4 input mixer[1] 0x0040 0000
Ch 4 input mixer[0] 0x0040 0000
0x62 IDF post scale 4 Post-IDF attenuation register 0x0000 0080
0x63–0xF7 Reserved(1) 0x0000 0000
0xF8 Device address enable register 4 Write F9 A5 A5 A5 in this register to enable write to device address update (0xF9) 0x0000 0000
0xF9 Device address Update Register 4 u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id (7:1) defines the new device address 0X0000 0036
0xFA–0xFF 4 Reserved(1) 0x0000 0000
(1) Reserved registers should not be accessed.
(2) ae stands for ∝ of energy filter, aa stands for ∝ of attack filter and ad stands for ∝ of decay filter and 1- ∝ = ω.

9.6.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5721. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of 192 fS and 384 fS only.

Table 5. Clock Control Register (0x00)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 fS = 32-kHz sample rate
0 0 1 Reserved(4)
0 1 0 Reserved(4)
0 1 1 fS = 44.1/48-kHz sample rate (1)
1 0 0 fs = 16-kHz sample rate
1 0 1 fs = 22.05/24-kHz sample rate
1 1 0 fs = 8-kHz sample rate
1 1 1 fs = 11.025/12-kHz sample rate
0 0 0 MCLK frequency = 64 × fS (2)
0 0 1 MCLK frequency = 128 × fS (2)
0 1 0 MCLK frequency = 192 × fS (3)
0 1 1 MCLK frequency = 256 × fS (1) (5)
1 0 0 MCLK frequency = 384 × fS
1 0 1 MCLK frequency = 512 × fS
1 1 0 Reserved(4)
1 1 1 Reserved(4)
0 Reserved(4) (1)
0 Reserved(4) (1)
(1) Default values are in bold.
(2) Only available for 44.1-kHz and 48-kHz rates.
(3) Rate only available for 32/44.1/48-kHz sample rates
(4) Reserved registers should not be accessed.
(5) Not available at 8 kHz

9.6.2 Device ID Register (0x01)

The device ID register contains the ID code for the firmware revision

Table 6. Device ID Register (0x01)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 Identification code

9.6.3 Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors.

Error Definitions:

  • MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
  • SCLK Error: The number of SCLKs per LRCLK is changing.
  • LRCLK Error: LRCLK frequency is changing.
  • Frame Slip: LRCLK phase is drifting with respect to internal frame sync.

Table 7. Error Status Register (0x02)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 - MCLK error
1 PLL autolock error
1 SCLK error
1 LRCLK error
1 Frame slip
1 Clip indicator
1 Overcurrent, overtemperature, overvoltage or undervoltage errors
0 Reserved
0 0 0 0 0 0 0 No errors (1)

9.6.4 System Control Register 1 (0x03)

The system control register 1 has several functions:

Bit D7: If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff < 1 Hz) for each channel is enabled (default).
Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the same time as the volume ramp defined in register 0x0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step volume ramp
Bits D1–D0: Select de-emphasis

Table 8. System Control Register 1 (0x03)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 PWM high-pass (dc blocking) disabled
1 PWM high-pass (dc blocking) enabled (1)
0 Reserved (1)
0 Soft unmute on recovery from clock error
1 Hard unmute on recovery from clock error (1)
0 Reserved (1)
0 Reserved (1)
0 Reserved(1)
0 0 No de-emphasis (1)
0 1 De-emphasis for fS = 32 kHz
1 0 De-emphasis for fS = 44.1 kHz
1 1 De-emphasis for fS = 48 kHz

9.6.5 Serial Data Interface Register (0x04)

As shown in Table 9, the TAS5721 supports nine serial data modes. The default is 24-bit, I2S mode,

Table 9. Serial Data Interface Control Register (0x04) Format

RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTH D7–D4 D3 D2 D1 D0
Right-justified 16 0000 0 0 0 0
Right-justified 20 0000 0 0 0 1
Right-justified 24 0000 0 0 1 0
I2S 16 000 0 0 1 1
I2S 20 0000 0 1 0 0
I2S (1) 24 0000 0 1 0 1
Left-justified 16 0000 0 1 1 0
Left-justified 20 0000 0 1 1 1
Left-justified 24 0000 1 0 0 0
Reserved 0000 1 0 0 1
Reserved 0000 1 0 1 0
Reserved 0000 1 0 1 1
Reserved 0000 1 1 0 0
Reserved 0000 1 1 0 1
Reserved 0000 1 1 1 0
Reserved 0000 1 1 1 1

9.6.6 System Control Register 2 (0x05)

When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute).

Table 10. System Control Register 2 (0x05)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 Mid-Z ramp disabled (1)
1 Mid-Z ramp enabled
0 Exit all-channel shutdown (normal operation)
1 Enter all-channel shutdown (hard mute)(1)
0 2.0 mode [2.0 BTL] (1)
1 2.1 mode [2 SE + 1 BTL]
0 ADR/FAULT pin is configured as to serve as an address input only(1)
1 ADR/FAULT pin is configured as fault output
0 0 0 0 Reserved (1)

9.6.7 Soft Mute Register (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

Table 11. Soft Mute Register (0x06)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 Reserved (1)
0 Soft unmute channel 3 (1)
1 Soft mute channel 3
0 Soft unmute channel 2 (1)
1 Soft mute channel 2
0 Soft unmute channel 1 (1)
1 Soft mute channel 1

9.6.8 Volume Registers (0x07, 0x08, 0x09, 0x0A)

Step size is 0.5 dB

Master volume – 0x07 (default is mute)
Channel-1 volume – 0x08 (default is 0 dB)
Channel-2 volume – 0x09 (default is 0 dB)
Channel-3 volume – 0x0A (default is 0 dB)

Table 12. Volume Registers (0x07, 0x08, 0x09, 0x0A)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 24 dB
0 0 1 1 0 0 0 0 0 dB (default for individual channel volume) (1)
1 1 1 1 1 1 1 0 –103 dB
1 1 1 1 1 1 1 1 Soft mute (default for the master volume)(1)

9.6.9 Volume Configuration Register (0x0E)

Bits D2–D0: Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows:
Sample Rate (KHz) Approximate Ramp Rate
8/16/32 125 us/step
11.025/22.05/44.1 90.7 us/step
12/24/48 83.3 us/step

Table 13. Volume Control Register (0x0E)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 1 0 Reserved (1)
0 Subchannel (ch4) volume = ch1 volume(1)(1)
1 Subchannel volume = register 0x0A(1)
0 Ch3 volume = ch2 volume(1)
1 Ch3 volume = register 0x0A
0 0 0 Volume slew 512 steps (43-ms volume ramp time at 48 kHz)
0 0 1 Volume slew 1024 steps (85-ms volume ramp time at 48 kHz) (1)
0 1 0 Volume slew 2048 steps (171- ms volume ramp time at 48 kHz)
0 1 1 Volume slew 256 steps (21-ms volume ramp time at 48 kHz)
1 X X Reserved
(1) Bits 6:5 can be changed only when volume is in MUTE [master volume = MUTE (register 0x07 = 0xFF)].

9.6.10 Modulation Limit Register (0x10)

The modulation limit is the maximum duty cycle of the PWM output waveform. It is important to note that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.

Table 14. Modulation Limit Register (0x10)

D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT
0 0 0 99.2%
0 0 1 98.4%
0 1 0 97.7% (1)
0 1 1 96.9%
1 0 0 96.1%
1 0 1 95.3%
1 1 0 94.5%
1 1 1 93.8%
0 0 0 0 0 RESERVED

9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

Table 15. Channel Interchannel Delay Register Format

SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs
0x11 1 0 1 0 1 1 Default value for channel 1 (1)
0x12 0 1 0 1 0 1 Default value for channel 2 (1)
0x13 1 0 1 0 1 1 Default value for channel 1 (1)
0x14 0 1 0 1 0 1 Default value for channel 2 (1)
RANGE OF VALUES FOR 0x11 - 0x14
0 0 0 0 0 0 Minimum absolute delay, 0 DCLK cycles
0 1 1 1 1 1 Maximum positive delay, 31 × 4 DCLK cycles
1 0 0 0 0 0 Maximum negative delay, –32 × 4 DCLK cycles
0 0 RESERVED

The ICD settings have high impact on audio performance (for example, dynamic range, THD+N, crosstalk, and so forth). Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown.

REGISTER AD MODE BD MODE
0x11 AC B8
0x12 54 60
0x13 AC A0
0x14 54 48

9.6.12 Pwm Shutdown Group Register (0x19)

Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D6 in the system control register.

This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D6 is set to 0 in system control register 2, 0x05).

Table 16. Shutdown Group Register

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 Reserved (1)
0 Reserved (1)
1 Reserved (1)
1 Reserved (1)
0 PWM channel 4 does not belong to shutdown group. (1)
1 PWM channel 4 belongs to shutdown group.
0 PWM channel 3 does not belong to shutdown group. (1)
1 PWM channel 3 belongs to shutdown group.
0 PWM channel 2 does not belong to shutdown group. (1)
1 PWM channel 2 belongs to shutdown group.
0 PWM channel 1 does not belong to shutdown group. (1)
1 PWM channel 1 belongs to shutdown group.

9.6.13 Start/stop Period Register (0x1A)

This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I2S clock stability.

Table 17. Start/Stop Period Register (0x1A)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 SSTIMER enabled(1)
1 SSTIMER disabled
0 0 Reserved (1)
0 0 No 50% duty cycle start/stop period
0 1 0 0 0 16.5-ms 50% duty cycle start/stop period
0 1 0 0 1 23.9-ms 50% duty cycle start/stop period
0 1 0 1 0 31.4-ms 50% duty cycle start/stop period
0 1 0 1 1 40.4-ms 50% duty cycle start/stop period
0 1 1 0 0 53.9-ms 50% duty cycle start/stop period
0 1 1 0 1 70.3-ms 50% duty cycle start/stop period
0 1 1 1 0 94.2-ms 50% duty cycle start/stop period
0 1 1 1 1 125.7-ms 50% duty cycle start/stop period(1)
1 0 0 0 0 164.6-ms 50% duty cycle start/stop period
1 0 0 0 1 239.4-ms 50% duty cycle start/stop period
1 0 0 1 0 314.2-ms 50% duty cycle start/stop period
1 0 0 1 1 403.9-ms 50% duty cycle start/stop period
1 0 1 0 0 538.6-ms 50% duty cycle start/stop period
1 0 1 0 1 703.1-ms 50% duty cycle start/stop period
1 0 1 1 0 942.5-ms 50% duty cycle start/stop period
1 0 1 1 1 1256.6-ms 50% duty cycle start/stop period
1 1 0 0 0 1728.1-ms 50% duty cycle start/stop period
1 1 0 0 1 2513.6-ms 50% duty cycle start/stop period
1 1 0 1 0 3299.1-ms 50% duty cycle start/stop period
1 1 0 1 1 4241.7-ms 50% duty cycle start/stop period
1 1 1 0 0 5655.6-ms 50% duty cycle start/stop period
1 1 1 0 1 7383.7-ms 50% duty cycle start/stop period
1 1 1 1 0 9897.3-ms 50% duty cycle start/stop period
1 1 1 1 1 13,196.4-ms 50% duty cycle start/stop period

9.6.14 Oscillator Trim Register (0x1B)

The TAS5721 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. TI recommends a reference resistor value of that shown in the Typical Application Diagrams. The circuit that uses this resistor should be calibrated or trimmed after each time the device is reset.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory. It is important to note that after writing the value 0x00 to the trim register, the register will repor the value 0xC0, to indicate the trim process is complete.

Table 18. Oscillator Trim Register (0x1B)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 Reserved (1)
0 Oscillator trim not done (read-only) (1)
1 Oscillator trim done (read only)
0 0 0 0 Reserved (1)
0 Select factory trim (Write a 0 to select factory trim; default is 1.)
1 Factory trim disabled (1)
0 Reserved (1)

9.6.15 BKND_ERR Register (0x1C)

When a backend error signal is received from the internal power stage, the power stage is reset stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting to restart the power stage.

Table 19. BKND_ERR Register (0x1C)(1)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 X Reserved
0 0 1 0 Set back-end reset period to 299 ms (1)
0 0 1 1 Set back-end reset period to 449 ms
0 1 0 0 Set back-end reset period to 598 ms
0 1 0 1 Set back-end reset period to 748 ms
0 1 1 0 Set back-end reset period to 898 ms
0 1 1 1 Set back-end reset period to 1047 ms
1 0 0 0 Set back-end reset period to 1197 ms
1 0 0 1 Set back-end reset period to 1346 ms
1 0 1 X Set back-end reset period to 1496 ms
1 1 X X
(1) This register can be written only with a non-reserved value. Also this register can be only be written once after the device is reset. If a different value is desired, the device must be reset before changing 0x1C again.

9.6.16 Input Multiplexer Register (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels.

Table 20. Input Multiplexer Register (0x20)

D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 - - - Reserved (1)
0 Polarity of Ch3 is not inverted
1 Polarity of Ch3 is inverted
0 Polarity of Ch2 is not inverted
1 Polarity of Ch2 is inverted
0 Polarity of Ch1 is not inverted
1 Polarity of Ch1 is inverted
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 Channel-1 AD mode (1)
1 Channel-1 BD mode
0 0 0 SDIN-L to channel 1 (1)
0 0 1 SDIN-R to channel 1
0 1 0 Reserved
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Ground (0) to channel 1
1 1 1 Reserved
0 Channel 2 AD mode (1)
1 Channel 2 BD mode
0 0 0 SDIN-L to channel 2
0 0 1 SDIN-R to channel 2 (1)
0 1 0 Reserved
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Ground (0) to channel 2
1 1 1 Reserved
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 1 1 1 0 1 1 1 Reserved (1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 Sub channel in 2.1 mode, AD modulation
1 Sub channel in 2.1 mode, BD modulation
0 1 1 1 - 0 1 0 Reserved (1)

9.6.17 Channel 4 Source Select Register (0x21)

This register selects the channel 4 source.

Table 21. Subchannel Control Register (0x21)

D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 0 0 0 Reserved(1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 1 0 0 0 0 1 Reserved (1)
0 (L + R)/2
1 Left-channel post-BQ (1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 1 1 Reserved (1)

9.6.18 PWM Output MUX Register (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin.

Bits D21–D20: Selects which PWM channel is output to OUT_A
Bits D17–D16: Selects which PWM channel is output to OUT_B
Bits D13–D12: Selects which PWM channel is output to OUT_C
Bits D09–D08: Selects which PWM channel is output to OUT_D

Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.
See Table 22 for details.

Table 22. PWM Output Mux Register (0x25)

D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 0 0 1 Reserved(1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 0 Reserved(1)
0 0 Multiplex PWM 1 to OUT_A (1)
0 1 Multiplex PWM 2 to OUT_A
1 0 Multiplex PWM 3 to OUT_A
1 1 Multiplex PWM 4 to OUT_A
0 0 Reserved (1)
0 0 Multiplex PWM 1 to OUT_B
0 1 Multiplex PWM 2 to OUT_B
1 0 Multiplex PWM 3 to OUT_B (1)
1 1 Multiplex PWM 4 to OUT_B
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 0 Reserved (1)
0 0 Multiplex PWM 1 to OUT_C
0 1 Multiplex PWM 2 to OUT_C(1)
1 0 Multiplex PWM 3 to OUT_C
1 1 Multiplex PWM 4 to OUT_C
0 0 Reserved (1)
0 0 Multiplex PWM 1 to OUT_D
0 1 Multiplex PWM 2 to OUT_D
1 0 Multiplex PWM 3 to OUT_D
1 1 Multiplex PWM 4 to OUT_D (1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 1 0 0 0 1 0 1 Reserved(1)

9.6.19 DRC Control (0x46)

Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.

Table 23. DRC Control Register

D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 Reserved (1)
0 Disable complementary (1–H) low-pass filter generation (1)
1 Enable complementary (1–H) low-pass filter generation
0
1
0 0 Reserved (1)
0 DRC2 turned OFF (1)
1 DRC2 turned ON
0 DRC1 turned OFF (1)
1 DRC1 turned ON

9.6.20 Bank Switch and EQ Control (0x50)

The bank switching feature is described in detail in section Bank Switching.

Table 24. Bank Switching Command

D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 32 kHz, does not use bank 3 (1)
1 32 kHz, uses bank 3
0 Reserved(1)
0 Reserved(1)
0 44.1/48 kHz, does not use bank 3 (1)
1 44.1/48 kHz, uses bank 3
0 16 kHz, does not use bank 3
1 16 kHz, uses bank 3 (1)
0 22.025/24 kHz, does not use bank 3
1 22.025/24 kHz, uses bank 3 (1)
0 8 kHz, does not use bank 3
1 8 kHz, uses bank 3 (1)
0 11.025 kHz/12, does not use bank 3
1 11.025/12 kHz, uses bank 3 (1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 32 kHz, does not use bank 2 (1)
1 32 kHz, uses bank 2
1 Reserved (1)
1 Reserved (1)
0 44.1/48 kHz, does not use bank 2
1 44.1/48 kHz, uses bank 2 (1)
0 16 kHz, does not use bank 2 (1)
1 16 kHz, uses bank 2
0 22.025/24 kHz, does not use bank 2 (1)
1 22.025/24 kHz, uses bank 2
0 8 kHz, does not use bank 2 (1)
1 8 kHz, uses bank 2
0 11.025/12 kHz, does not use bank 2 (1)
1 11.025/12 kHz, uses bank 2
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 32 kHz, does not use bank 1
1 32 kHz, uses bank 1 (1)
0 Reserved(1)
0 Reserved(1)
0 44.1/48 kHz, does not use bank 1 (1)
1 44.1/48 kHz, uses bank 1
0 16 kHz, does not use bank 1 (1)
1 16 kHz, uses bank 1
0 22.025/24 kHz, does not use bank 1 (1)
1 22.025/24 kHz, uses bank 1
0 8 kHz, does not use bank 1 (1)
1 8 kHz, uses bank 1
0 11.025/12 kHz, does not use bank 1 (1)
1 11.025/12 kHz, uses bank 1
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 EQ ON
1 EQ OFF (bypass BQ 0-7 of channels 1 and 2)
0 Reserved (1)
0 Ignore bank-mapping in bits D31–D8.Use default mapping. (1)
1 Use bank-mapping in bits D31–D8.
0 L and R can be written independently. (1)
1 L and R are ganged for EQ biquads; a write to left-channel BQ is also written to right-channel BQ. (0x29–0x2F is ganged to 0x30–0x36.Also 0x58–0x5B is ganged to 0x5C–0x5F)
0 Reserved (1)
0 0 0 No bank switching. All configuration of the BiQuads are applied directly to the DAP (1)
0 0 1 Configure bank 1 (32 kHz by default)
0 1 0 Configure bank 2 (44.1/48 kHz by default)
0 1 1 Configure bank 3 (other sample rates by default)
1 0 0 Automatic bank selection
1 0 1 Reserved
1 1 X Reserved

All DAP coefficients are 3.23 format unless specified otherwise.