SLLU149E June   2011  – February 2016 TUSB7320 , TUSB7340

 

  1.   TUSB73x0 Board Design and Layout Guidelines
    1.     Trademarks
    2.     Related Documentation
  2. 1 Typical System Implementation
    1. 1.1 Overview
  3. 2 Power
    1. 2.1 Overview
    2. 2.2 Digital Supplies
    3. 2.3 Analog Supplies
    4. 2.4 Ground Terminal
    5. 2.5 Capacitor Selection Recommendations
    6. 2.6 USB VBUS
  4. 3 Device Reset
    1. 3.1 Overview
  5. 4 General High Speed Layout Guidelines
    1. 4.1 Printed Circuit Board Stackup (FR-4 Example)
    2. 4.2 Return Current and Plane References
    3. 4.3 Split Planes – What to Avoid
    4. 4.4 Avoiding Crosstalk
  6. 5 USB Connection
    1. 5.1 Overview
    2. 5.2 Internal Chip Trace Length Mismatch
    3. 5.3 High-Speed Differential Routing
    4. 5.4 SuperSpeed Differential Routing
  7. 6 Package and Breakout
    1. 6.1 Package Drawing
    2. 6.2 Routing Between Pads
    3. 6.3 Pads
    4. 6.4 Land Pattern Recommendation
    5. 6.5 Solder Stencil
  8. 7 PCI Express Connection
    1. 7.1 Internal Chip Trace Length Mismatch
    2. 7.2 Transmit and Receive Links
    3. 7.3 PCI-Express Reference Clock Input
    4. 7.4 PCI Express Reset
    5. 7.5 PCI Express WAKE/CLKREQ
      1. 7.5.1 Leakage Current on Pins WAKE# and CLKREQ#
      2. 7.5.2 Recommendations
  9. 8 Wake from S3
    1. 8.1 Overview
  10. 9 Device Input Clock
    1. 9.1 Overview
  11. 10JTAG Interface
    1. 10.1 Overview
  12. 11Differential Pair ESD Protection
    1. 11.1 Overview
  13. 12SuperSpeed Redriver
    1. 12.1 Overview
  14. 13SMI Pin Implementation
    1. 13.1 Overview
  15. 14Schematics
    1. 14.1 Overview
    2. 14.2 TUSB7320 DEMO EVM REVB Schematics
    3. 14.3 TUSB7340 DEMO EVM REVB Schematics
  16.   Revision History

7.5.2 Recommendations

Care should be taken during 'Bed of Nail' or 'In Circuit Test' so that a constant current source is not used to test continuity on the WAKE# pin. A negative current test is recommended as there is a ground diode on the device that will clamp the voltage at the WAKE# and CLKREQ# pins.

Avoid using a handheld multimeter to test continuity of the WAKE# and CLKREQ# pins. Many multimeters use a constant current source that could be as high as 1 mA which could expose WAKE# and CLKREQ# pins to the high voltage.

On running projects that are already in production, if the stress voltage on the WAKE# pin of TUSB7320
< 4.6 V when VDD33 is zero, there is no risk on the shipping platform.

On new projects in design or projects that are not in mass production yet, TI suggests ODMs adding a FET (make sure parasitic diode is reversed bias) and 10-kΩ pull up resistor on WAKE# to prevent overstress (see Figure 7-3). Also, due to an erratum on TUSB73x0, a 0.001-µF capacitor to ground is required on the WAKE# and CLKREQ# signals. The rise time must be greater than 450 ns. See the errata (SLLZ067) for a more detailed explanation.

connection_wake_llu149.gif
1. Power Good is a 3.3-V signal asserted high when VDD33 is at its valid operating voltage (see Recommended Operating Conditions table in the Data Manual, SLLSE76).
2. N-Channel MOSFET 2N7002 or 2N7002K are suitable devices for use in the circuit.
Figure 7-3 Connection of WAKE#

In all projects going forward, do not use constant current during 'In Circuit Test'. If that is not possible, omit WAKE# and CLKREQ# pins from the 'ICT'.