SLLU149E June   2011  – February 2016 TUSB7320 , TUSB7340

 

  1.   TUSB73x0 Board Design and Layout Guidelines
    1.     Trademarks
    2.     Related Documentation
  2. 1 Typical System Implementation
    1. 1.1 Overview
  3. 2 Power
    1. 2.1 Overview
    2. 2.2 Digital Supplies
    3. 2.3 Analog Supplies
    4. 2.4 Ground Terminal
    5. 2.5 Capacitor Selection Recommendations
    6. 2.6 USB VBUS
  4. 3 Device Reset
    1. 3.1 Overview
  5. 4 General High Speed Layout Guidelines
    1. 4.1 Printed Circuit Board Stackup (FR-4 Example)
    2. 4.2 Return Current and Plane References
    3. 4.3 Split Planes – What to Avoid
    4. 4.4 Avoiding Crosstalk
  6. 5 USB Connection
    1. 5.1 Overview
    2. 5.2 Internal Chip Trace Length Mismatch
    3. 5.3 High-Speed Differential Routing
    4. 5.4 SuperSpeed Differential Routing
  7. 6 Package and Breakout
    1. 6.1 Package Drawing
    2. 6.2 Routing Between Pads
    3. 6.3 Pads
    4. 6.4 Land Pattern Recommendation
    5. 6.5 Solder Stencil
  8. 7 PCI Express Connection
    1. 7.1 Internal Chip Trace Length Mismatch
    2. 7.2 Transmit and Receive Links
    3. 7.3 PCI-Express Reference Clock Input
    4. 7.4 PCI Express Reset
    5. 7.5 PCI Express WAKE/CLKREQ
      1. 7.5.1 Leakage Current on Pins WAKE# and CLKREQ#
      2. 7.5.2 Recommendations
  9. 8 Wake from S3
    1. 8.1 Overview
  10. 9 Device Input Clock
    1. 9.1 Overview
  11. 10JTAG Interface
    1. 10.1 Overview
  12. 11Differential Pair ESD Protection
    1. 11.1 Overview
  13. 12SuperSpeed Redriver
    1. 12.1 Overview
  14. 13SMI Pin Implementation
    1. 13.1 Overview
  15. 14Schematics
    1. 14.1 Overview
    2. 14.2 TUSB7320 DEMO EVM REVB Schematics
    3. 14.3 TUSB7340 DEMO EVM REVB Schematics
  16.   Revision History

3.1 Overview

There is no GRST# timing constraint with respect to the power supplies, other than it should not be deasserted until the power supplies are stable.

However, extreme care must be taken if a passive reset is used, such as using the internal GRST# pull up or an external RC circuit, to ensure that the GRST# does not deassert until the 3.3-V and 1.1-V rails are within 10% of nominal. If the 3.3-V power ramps before the 1.1-V supply, and GRST# is deasserted, the device I/O is in an undefined state before the core logic is active. This allows the potential for the GRST# I/O cell to incorrectly configure as an output and drive the GRST# signal high until the core logic is powered on and correctly configures the cell.

It is highly recommended that the GRST# input be connected to a power good output from a power supply to ensure that it does not deassert until both the 3.3-V and 1.1-V power rails are within 10% of their nominal value. The recommended sequence is to have the 3.3-V feed a 1.1-V regulator and then use the 1.1-V Power Good signal to drive GRST# as outlined below.

regulator_llu149.gifFigure 3-1 1.1-V Regulator