SLLA565 September   2021 TUSB1044

 

  1.   Trademarks
  2. 1Introduction
  3. 2TUSB1044 Configuration and Control Implementation
    1. 2.1 TUSB1044 Four-Level Pins
      1. 2.1.1 I2C_EN
      2. 2.1.2 VIO_SEL
      3. 2.1.3 UEQ[1:0] and DEQ[1:0]
      4. 2.1.4 CFG[1:0]
    2. 2.2 TUSB1044 Two-Level Pins
      1. 2.2.1 FLIP, CTL0, and CTL1
      2. 2.2.2 DIR0 and DIR1
      3. 2.2.3 SWAP
      4. 2.2.4 HPDIN
      5. 2.2.5 SLP_S0#
  4. 3TUSB1044 I2C Mode Implementation
    1. 3.1 TUSB1044 Operating Mode Configuration, General_1 Register, 0x0A
    2. 3.2 VOD Configuration, General_3 Register 0x0C
    3. 3.3 Upstream and Downstream Equalization Configuration Registers, UFP1_EQ, UFP2_EQ, DFP1_EQ, and DFP2_EQ Registers 0x10, 0x11, 0x20, 0x21
  5. 4Benefits of Using the I2C Mode Control
  6. 5TUSB1044 Host Implementation Example
  7. 6TPS6598X, TPS6599X Based I2C Control and Tuning
    1. 6.1 Enable PD Controller I2C Control of External Slaves
    2. 6.2 Example of I2C Configuration Upon PD Controller PoR Event and Detach Event
    3. 6.3 Example of I2C Configuration Upon Cable-Orientation Event and DP Configuration Event
    4. 6.4 Notes for Application
  8. 7References

3.2 VOD Configuration, General_3 Register 0x0C

General_3 Register 0x0C describes how the VOD and DC Gain are configured through the register.

Specifically, for VOD definition:

  • 0x0C bit[6] defines ‘0’ for VOD/DC Gain set by CFG pins and ‘1’ override by I2C
  • 0x0C bit[5:4] defines VOD/DC Gain setting mapped to CFG1 (0h=’0’, 1h=’R’, 2h=’F’, 3h=’1’)
  • 0x0C bit[3:2] defines VOD/DC Gain setting mapped to CFG0 (0h=’0’, 1h=’R’, 2h=’F’, 3h=’1’)
  • 0x0C bit[1:0] defined as 0h (as DIR_SEL, for notebook as USB and DP source)

Table 3-4 shows the register 0x0C bit definition.

Table 3-4 Register 0x0C Bit Definition
Bit Field Type Reset Description
7 RESERVED R 0h

Reserved
6 VOD_DCGAIN_OVERRIDE R/W 0h

Setting of this field will allow software to use VOD linearity range and DC gain settings from registers instead of value sampled from pins

0h = VOD linearity and DC gain settings based on sampled CFG[2:1] pins.

1h = EQ settings based on programmed value of each VOD linearity and DC Gain registers.
5-2 VOD_DCGAIN_SEL R/W 0h

Field selects VOD linearity range and DC gain for all the channels and in all directions. When VOD_DCGAIN_OVERRIDE = 0b, this field reflects the sampled state of CFG[1:0] pins. When VOD_DCGAIN_OVERRIDE = 1b software can change the VOD linearity range and DC gain for all the channels and in all directions based on value written to this field. Each CFG is a 2-bit value. The register-to-CFG1/0 mapping is: [5:2] = {CFG1[1:0], CFG0[1:0]} where CFGx[1:0] mapping is:

0h = 0

1h = R

2h = F

3h = 1
1-0 DIR_SEL R/W 0h

Sets the operation mode.

0h = USB + DP Alt Mode Source

1h = USB + DP Alt Mode Sink.

2h = USB + Custom Alt Mode Source

3h = USB + Custom Alt Mode Sink.