UFP2_EQ and UFP1_EQ Register 0x10, 0x11, General_1
Register 0x20, 0x21 are defined to be registers for EQ
configuration.
- 0x10 bit[7:4] defines EQ setting for UTx2
channel
- 0x10 bit[3:0] defines EQ setting for URx2
channel
- 0x11 bit[7:4] defines EQ setting for UTx1
channel
- 0x11 bit[3:0] defines EQ setting for URx1
channel
- 0x20 bit[7:4] defines EQ setting for DTx2
channel
- 0x20 bit[3:0] defines EQ setting for DRx2
channel
- 0x21 bit[7:4] defines EQ setting for DTx1
channel
- 0x21 bit[3:0] defines EQ setting for DRx1
channel