SFFS594 December 2023 TPSI3100-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the TPSI310x-Q1 and TPSI310x family. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-2.
Table 4-1 TI Classification of Failure
Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the TPSI310x-Q1 and TPSI310x pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the data sheets.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Device in normal operation prior to any open or short condition being applied to the respective pin
- EN set to a static logic low or high (VDRV asserted low or high respectively)
- CE set to a static logic low or high.
- Opens or shorts occur relative to primary and secondary sides of the device and is a static event
Table 4-2 Pin FMA for Device Pins
Short-Circuited to VSSP or VSSS
| Pin Name | Pin No. | Ground | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| EN | 1 | VSSP | VDRV asserted low. | B |
| CE | 2 | VSSP | Device in standby. No power transfer. VDDH and VDDM rail discharge. VDRV asserted low with active clamp enabled. | B |
| VDDP | 4 | VSSP | No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. | B |
| PGOOD | 5 | VSSP | PGOOD asserted low. If PGOOD not used, tie to VSSP. | B |
| FLT1 | 6 | VSSP | FLT1 asserted low. If FLT1 not used, tie to VSSP. | B |
| ALM1 | 7 | VSSP | ALM1 asserted low. If ALM1 not used, tie to VSSP. | B |
| RESP | 10 | VSSS | Comparator de-glitch is set to minimum value which may be less than the application requirements. | C |
| ALM1_CMP | 11 | VSSS | ALM1 open-drain output is high-impedance. If ALM1_CMP not used, tie to VSSS. | B |
| FLT1_CMP | 12 | VSSS | FLT1 open-drain output is high-impedance. If FLT1_CMP not used, tie to VSSS. | B |
| VDDM | 13 | VSSS | VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. | B |
| VDDH | 15 | VSSS | VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. | B |
| VDRV | 16 | VSSS | If VDRV was high, VDDH and VDDM rail collapse. VDRV asserts low with active clamp enabled. If VDRV was low, no effect. | B |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN | 1 | VDRV asserted low. EN pin has an internal resistive pull-down to VSSP. | B |
| CE | 2 | Device powers off. VDDH and VDDM rails discharge. VDRV asserted low. CE pin has an internal resistive pull-down to VSSP. | B |
| VSSP | 3 | Device has additional ground path through pin 8 (VSSP). | C |
| VDDP | 4 | No power transfer. VDDH and VDDM rail collapse. VDRV asserted low with active clamp enabled. | B |
| PGOOD | 5 | If PGOOD unused, no effect. If PGOOD used, PGOOD asserted high is indicated to the system regardless of actual status. | B |
| FLT1 | 6 | If FLT1 unused, no effect. If FLT1 used, FLT1 asserted high is indicated to the system regardless of actual status of FLT1_CMP comparator output. | B |
| ALM1 | 7 | If ALM1 unused, no effect. If ALM1 used, ALM1 asserted high is indicated to the system regardless of actual status of ALM1_CMP comparator output. | B |
| VSSP | 8 | Device has additional ground path through pin 3 (VSSP). | C |
| VSSS | 9 | Device has ground path through pin 14 (VSSS). Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows state of EN logic level. | C |
| RESP | 10 | Comparator de-glitch is set to maximum value which may be more than the application requirements. | B |
| ALM1_CMP | 11 | ALM1_CMP pin has a weak internal resistive pull-down to VSSS and can be susceptible to switching noise causing false alarm indications. If ALM1_CMP not used, tie to VSSS | B |
| FLT1_CMP | 12 | FLT1_CMP pin has a weak internal resistive pull-down to VSSS and can be susceptible to switching noise causing false alarm indications. If FLT1_CMP not used, tie to VSSS | B |
| VDDM | 13 | VDDH and VDDM can collapse under loading or switching events. | B |
| VSSS | 14 | Device has ground path through pin 9 (VSSS). Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows state of EN logic level. | C |
| VDDH | 15 | VDDH can collapse under loading or switching events. | B |
| VDRV | 16 | No drive to external switch. External switch gate control can float dependent upon application circuitry. | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to
Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| VDRV | 16 | VDDH | If VDRV was low, VDDH and VDDM rail collapse. VDRV remains low with active clamp enabled. If VDRV was high, no effect. | B |
| FLT1_CMP | 12 | VDDM | If strength of signal driving FLT1_CMP is high, VDDM and VDDH rails may collapse, and VDRV will be asserted low. Power transfer continues, although at a much lower amount. If strength of signal driving FLT1_CMP is weak, FLT1_CMP comparator threshold may be reached causing VDRV to be asserted low. | B |
| FLT1_CMP | 12 | ALM1_CMP | FLT1_CMP comparator threshold may be reached causing VDRV to be asserted low, along with FLT1 asserting low. Similarly, if ALM1_CMP threshold reached, ALM1 asserts low. | B |
| ALM1_CMP | 11 | RESP | Depending on strength of signal driving ALM1_CMP, ALM1_CMP threshold may not be reached, and no ALM1 events will occur. De-glitch of comparators may increase or decrease depending on strength of signal driving ALM1_CMP. | B |
| EN | 1 | CE | EN can be tied to CE in the application if desired. | D |
| PGOOD | 5 | FLT1 | Electrical ORing of PGOOD and FLT1open-drain outputs. All status indicators can be tied in the application if desired. | D |
| FLT1 | 6 | ALM1 | Electrical ORing of FLT1 and ALM1open-drain outputs. All status indicators can be tied in the application if desired. | D |
Table 4-5 Pin FMA for Device Pins Short-Circuited to
VDDP
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN | 1 | EN can be tied to VDDP in the application if desired. | D |
| CE | 2 | CE can be tied to VDDP in the application if desired. Device powers up depending on voltage level of VDDP. | D |
| PGOOD | 5 | Potential high current from VDDP while PGOOD asserted low. Device may thermal cycle or may get damaged. | A |
| FLT1 | 6 | Potential high current from VDDP while FLT1 asserted low. Device may thermal cycle or may get damaged. | A |
| ALM1 | 7 | Potential high current from VDDP while ALM1 asserted low. Device may thermal cycle or may get damaged. | A |