ZHCSQE6 October   2023 UCC27332-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Power On Reset
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
    4. 7.4 Device Functional Modes
  9. 8  Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Driving MOSFET
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input-to-Output Configuration
          2. 8.2.1.2.2 Input Threshold Type
          3. 8.2.1.2.3 VDD Bias Supply Voltage
          4. 8.2.1.2.4 Peak Source and Sink Currents
          5. 8.2.1.2.5 Enable and Disable Function
          6. 8.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 8.2.1.2.7 Power Dissipation
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Consideration
  10. 9 Device and Documentation Support
    1. 9.1 第三方产品免责声明
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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6.6 Switching Characteristics

Unless otherwise noted, VDD = VEN = 4.5 V to 18 V, TA = TJ = –40°C to 125°C, 1-µF capacitor from VDD to GND, No load on the output. Typical condition specifications are at 25°C (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR Rise time CLOAD = 10 nF, 20% to 80%, VIN = 0 V to 5V

16

 30 ns
tF Fall time CLOAD = 10 nF, 80% to 20%, VIN = 0 V to 5V

11

 28 ns
tD1 Turnon propagation delay CLOAD = 10 nF, VIN_H of the input rise to 20% of output rise, VIN =0 V to 5V, Fsw=500kHz, 50% duty cycle 25 60 ns
tD2 Turn-off propagation delay CLOAD = 10 nF, VIN_L of the input fall to 80% of output fall, VIN =0 V to 5V, Fsw=500kHz, 50% duty cycle 34 65 ns
tPD_EN Enable propagation delay CLOAD = 10 nF, VEN_H of the enable rise to 20% of output rise, VIN =0 V to 5V, Fsw=500kHz, 50% duty cycle 27 40 ns
tPD_DIS Disable propagation delay CLOAD = 10 nF, VEN_L of the enable fall to 80% of output fall, VIN =0 V to V, Fsw=500kHz, 50% duty cycle 28 64 ns
tPWmin Minimum input pulse width that passes to the output CLOAD = 10 nF, VIN =0 V to 5V, Fsw=500kHz, Vo > 1.5 V 30.5 ns
(1) Switching parameters are not tested in production.