10.1 Layout Guidelines

To improve the switching characteristics and efficiency of a design, the following layout rules must be followed.

• Locate the driver as close as possible to the MOSFETs.
• Locate the V_DD and V_HB (bootstrap) capacitors as close as possible to the driver.
• Pay close attention to the GND trace. Use the thermal pad of the DDA package as GND by connecting it to the V_SS pin (GND).

NOTE

The GND trace from the driver goes directly to the source of the MOSFET, but must not be in the high-current path of the MOSFET(S) drain or source current.

• Use similar rules for the HS node as for GND for the high-side driver.
• Use wide traces for LO and HO closely following the associated GND or HS traces. Where possible, widths of 60 mil to 100 mil are preferred.
• Use two or more vias if the driver outputs or SW node must be routed from one layer to another. For GND, consider the number of vias of the thermal pad requirements of the thermal pad requirements as well as parasitic inductance.
• Avoid L_I and H_I (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high-impedance leads.
• Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system.

10.2 Layout Example

Figure 38. Example Component Placement

10.3 Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 1.

Use Equation 2 to calculate the DC portion of the power dissipation (PDC).

The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through, and so forth). The UCC2720x-Q1 device features very low quiescent currents (see Electrical Characteristics) and contain internal logic to eliminate any shoot through in the output driver stage. Thus the effect of the PDC on the total power dissipation within the gate driver can be safely assumed to be negligible. The power dissipated in the gate-driver package during switching (PSW) depends on the following factors:

• Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to input bias supply voltage V_DD)
• Switching frequency
• Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 3.
Equation 3. EG = ½C_LOAD × V_DD²
where
• C_LOAD is load capacitor
• V_DD is bias voltage feeding the driver

There is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. This leads to a total power loss given by Equation 4.

The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when switching a capacitor which is calculated using the equation Q_G = C_LOAD × V_DD to provide Equation 5 for power.

This power P_G is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on and off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor.