11.1 Layout Guidelines

As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground signal. Separating the high di/dt induced noise on the power ground from the low current quiet signal ground is required for adequate noise immunity. As shown Figure 38, the bypass capacitors on VCC and VREF have one end located in close proximity to their associated pins and the other ends are returned directly to the GND pin or to the portion of the ground plane associated with the low level GND signal and not to the high current power return. Low-ESR type ceramic capacitors are recommended as bypass capacitors.

The gate-drive output signals (GD1 and GD2) can cause interference on the low-level inputs (CL and CS) and for this reason must be routed as far as possible away from them and have short direct paths to the gate-drive transformer. In general any slow-changing analog signals must be routed away from high-speed digital signals.

Timing resistors FMIN and FMAX must be placed as close as possible to the pins on the UCC25710.

11.2 Layout Example

Figure 38. Layout Example for UCC25710