ZHCSHR5C March   2018  – September 2019 TUSB1064

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      TUSB1064 使用示例
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 ELECTRICAL CHARACTERISTICS
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 11. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 12. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 13. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 14. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 15. DisplayPort Control/Status Registers (0x13)
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 16. USB3.1 Control/Status Registers (0x20)
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 17. USB3.1 Control/Status Registers (0x21)
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
        1. Table 18. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]

Figure 22. DisplayPort Control/Status Registers (0x13)
7 6 5 4 3 2 1 0
AUX_SNOOP_DISABLE Reserved AUX_SBU_OVR DP3_DISABLE DP2_DISABLE DP1_DISABLE DP0_DISABLE
R/W R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. DisplayPort Control/Status Registers (0x13)

Bit Field Type Reset Description
7 AUX_SNOOP_DISABLE R/W 0 0 – AUX snoop enabled. (Default)
1 – AUX snoop disabled.
6 Reserved R 0 Reserved
5:4 AUX_SBU_OVR R/W 00 This field overrides the AUXp or AUXn to SBU1 or SBU2 connect and disconnect based on CTL1 and FLIP. Changing this field to 2’b01 or 2'b10 will allow traffic to pass through AUX to SBU regardless of the state of CTLSEL1 and FLIPSEL register
00 – AUX to SBU connect/disconnect determined by CTLSEL1 and FLIPSEL (Default)
01 – AUXn -> SBU1 and AUXp -> SBU2 connection always enabled.
10 – AUXn -> SBU2 and AUXp -> SBU1 connection always enabled.
11 – AUX to SBU open.
3 DP3_DISABLE R/W 0 When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 3 functionality.
0 – DP Lane 3 Enabled (default)
1 – DP Lane 3 Disabled.
2 DP2_DISABLE R/W 0 When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 2 functionality.
0 – DP Lane 2 Enabled (default)
1 – DP Lane 2 Disabled.
1 DP1_DISABLE R/W 0 When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 1 functionality.
0 – DP Lane 1 Enabled (default)
1 – DP Lane 1 Disabled.
0 DP0_DISABLE R/W 0 DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 1’b0, changes to this field will have no effect on lane 0 functionality.
0 – DP Lane 0 Enabled (default)
1 – DP Lane 0 Disabled.