ZHCSHR5C March   2018  – September 2019 TUSB1064

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      TUSB1064 使用示例
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 ELECTRICAL CHARACTERISTICS
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 11. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 12. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 13. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 14. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 15. DisplayPort Control/Status Registers (0x13)
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 16. USB3.1 Control/Status Registers (0x20)
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 17. USB3.1 Control/Status Registers (0x21)
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
        1. Table 18. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 ELECTRICAL CHARACTERISTICS

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
PCC-ACTIVE-USB Average active power in USB-only mode while in U0. CTL1 = L; CTL0 = H; Link in U0 at 10Gbps; 330 mW
PCC-ACTIVE-USB-DP Average active power in USB + 2 lane DP mode. CTL1 = H; CTL0 = H; USB in U0 at 10Gbps;  DP at 8.1Gbps; 660 mW
PCC-ACTIVE-DP Average active power in 4 lane DP mode. CTL1 = H; CTL0 = L; Four DP lanes at 8.1Gbps 660 mW
PCC-NC-USB Average power in USB mode while in disconnect state. CTL1 = L; CTL0 = H; No USB device detected; 2.5 mW
PCC-U2U3 Average power in USB mode while in U2/U3 state CTL1 = L; CTL0 = H; Link in U2 or U3; 2.5 mW
PCC-SHUTDOWN Average power in Shutdown mode. CTL1 = L; CTL0 = L; I2C_EN = "0"; 0.7 mW
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
IIH High-level input current VCC = 3.6 V; VIN = 3.6 V 20 80 µA
IIL Low-level input current VCC = 3.6 V; VIN = 0 V -160 -40 µA
4-Level VTH Threshold 0 / R VCC = 3.3 V 0.55 V
Threshold R/ Float VCC = 3.3 V 1.65 V
Threshold Float / 1 VCC = 3.3 V 2.7 V
RPU Internal pull up resistance 45 kΩ
RPD Internal pull-down resistance 95 kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, EN, HPDIN) CTL1, CTL0 and FLIP are Failsafe
VIH High-level input voltage 2 3.6 V
VIL Low-level input voltage 0 0.8 V
RPD Internal pull-down resistance for CTL1, CTL0, FLIP, and EN.     500 kΩ
IIH High-level input current VIN = 3.6 V -25 25 µA
IIL Low-level input current VIN = GND, VCC = 3.6 V -25 25 µA
I2C Control Pins SCL, SDA
VIH High-level input voltage I2C_EN ! = 0 0.7 x VI2C 3.6 V
VIL Low-level input voltage I2C_EN ! = 0 0 0.3 × VI2C V
VOL Low-level output voltage I2C_EN ! = 0; IOL = 3 mA 0 0.4 V
IOL Low-level output current I2C_EN ! = 0; VOL = 0.4 V 20 mA
Ii_I2C Input current on SDA pin 0.1 × VI2C < Input voltage < 3.3 V -10 10 µA
Ci_I2C Input capacitance 10 pF
USB Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
VRX-DIFF-PP Input differential peak-peak voltage swing linear dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 2000 mVpp
VRX-DC-CM Common-mode voltage bias in the receiver (DC) 0 V
RRX-DIFF-DC Differential input impedance (DC) Present after a USB3.1 device is detected on TXP/TXN 72 120 Ω
RRX-CM-DC Receiver DC Common Mode impedance Present after a USB3.1 device is detected on TXP/TXN 18 30 Ω
ZRX-HIGH-IMP-DC-POS Common-mode input impedance with termination disabled (DC) Present when no USB3.1 device is detected on TXP/TXN. Measured over the range of 0-500 mV with respect to GND. 25 kΩ
VSIGNAL-DET-DIFF-PP Input Differential peak-to-peak Signal Detect Assert Level at 10Gbps, No loss and bit rate PRBS7 pattern 79 mV
VRX-IDLE-DET-DIFF-PP Input Differential peak-to-peak Signal Detect De-assert Level at 10 Gbps, No loss and bit rate PRBS7 pattern 58 mV
VRX-LFPS-DET-DIFF-PP Low-frequency Periodic Signaling (LFPS) Detect Threshold Below the minimum is squelched. 100 300 mV
CRX RX input capacitance to GND At 2.5 GHz 0.5 1 pF
RLRX-DIFF Differential Return Loss 50 MHz – 1.25 GHz at 90 Ω -13 dB
RLRX-DIFF Differential Return Loss 5 GHz at 90 Ω -9 dB
RLRX-CM Common Mode Return Loss 50 MHz – 5 GHz at 90 Ω -8 dB
EQSSP Receiver equalization SSEQ[1:0] and EQ[1:0] at 5 GHz. 12 dB
USB Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX-DIFF-PP Transmitter dynamic differential voltage swing range.     1300   mVpp
VTX-RCV-DETECT Amount of voltage change allowed during Receiver Detection at 3.3 V     600 mV
VTX-CM-IDLE-DELTA Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS measured at the connector side of the AC coupling caps with 50 Ω load -600   600 mV
VTX-DC-CM Common-mode voltage bias in the transmitter (DC)   0   2 V
VTX-CM-AC-PP-ACTIVE Tx AC Common-mode voltage active At 3.3V; Max mismatch from Txp+Txn for both time and amplitude     100 mVpp
VTX-IDLE-DIFF-AC-PP AC Electrical idle differential peak-to-peak output voltage At package pins 0   10 mV
VTX-IDLE-DIFF-DC DC Electrical idle differential output voltage At package pins after low-pass filter to remove AC component 0   14 mV
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute DC common mode voltage between U1 and U0 At package pin     200 mV
CTX TX input capacitance to GND At 2.5 GHz     1.25 pF
RTX-DIFF Differential impedance of the driver   75   120 Ω
CAC-COUPLING AC Coupling capacitor   75   265 nF
RTX-CM Common-mode impedance of the driver Measured with respect to AC ground over 0-500 mV 18   30 Ω
ITX-SHORT TX short circuit current TX+/- shorted to GND     67 mA
RLTX-DIFF Differential Return Loss 50 MHz – 1.25 GHz at 90 Ω   -17   dB
RLTX-DIFF-5G Differential Return Loss 5 GHz at 90 Ω   -12   dB
RLTX-CM Common Mode Return Loss 50 MHz – 5 GHz at 90 Ω   -9   dB
AC Electrical Characteristics for USB and DP
Crosstalk Differential Cross Talk between TX and RX signal Pairs at 5 GHz   -27   dB
GLF Low-frequency voltage gain.    at 100 MHz, 600 mVpp VID -2.5 0.5 3.5 dB
GLF_LFPS_TX1/2 Low-frequency voltage gain for SSTX->TX1/TX2 path.     at 10 to 50MHz sine wave; 1.0Vpp VID; EQ = 0; FLIP = 0 and 1; 0 0.8 1.6 dB
CP1 dB-LF Low-frequency 1-dB compression point at 100 MHz, 200 mVpp < VID < 2000 mVpp 1000 mVpp
CP1 dB-HF High-frequency 1-dB compression point at 5 GHz, 200 mVpp < VID < 2000 mVpp   770   mVpp
fLF Low-frequency cutoff 200 mVpp < VID < 2000 mVpp   20 50 kHz
DJ_10G TX output deterministic jitter 200 mVpp < VID < 2000 mVpp, PRBS7, 10 Gbps   0.10   UIpp
DJ_8.1G TX output deterministic jitter 200 mVpp < VID < 2000 mVpp, PRBS7, 8.1 Gbps   0.08   UIpp
TJ_10G TX output total jitter 200 mVpp < VID < 2000 mVpp, PRBS7, 10 Gbps   0.13   UIpp
TJ_8.1G TX output total jitter 200 mVpp < VID < 2000 mVpp, PRBS7, 8.1 Gbps   0.12   UIpp
DisplayPort Receiver (TX1P/N, TX2P/N, RX1P/N, RX2P/N)
VID_PP Peak-to-peak input differential dynamic voltage range     2000   mV
VIC Input Common Mode Voltage   0 V
CAC AC coupling capacitance   75   265 nF
EQDP Receiver Equalizer DPEQ1, DPEQ0 at 4.05 GHz   12   dB
dR Data rate HBR3     8.1 Gbps
Rti Input Termination resistance   80 100 120 Ω
DisplayPort Transmitter (DP[3:0]P/N)
VTX-DIFFPP VOD dynamic range     1300   mV
ITX-SHORT TX short circuit current TX+/- shorted to GND     67 mA
AUXP/N and SBU1/2
RON Output ON resistance VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP; VIN = 2.7 V to 3.6 V for AUXN   5 10 Ω
RON-MISMATCH ΔON resistance mismatch within pair VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP; VIN= 2.7 V to 3.6 V for AUXN     1 Ω
RON_FLAT ON resistance flatness (RONmax–RON min) measured at identical VCC and temperature VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP; VIN = 2.7 V to 3.6 V for AUXN     2 Ω
VAUXP_DC_CM AUX Channel DC common mode voltage for AUXP and SBU2. VCC = 3.3 V 0   0.4 V
VAUXN_DC_CM AUX Channel DC common mode voltage for AUXN and SBU1 VCC = 3.3 V 2.7   3.6 V
CAUX_ON ON-state capacitance VCC = 3.3 V; CTL1 = 1; VIN = 0 V or 3.3 V   4 7 pF
CAUX_OFF OFF-state capacitance VCC = 3.3 V; CTL1 = 0; VIN = 0 V or 3.3 V   3 6 pF