ZHCSHJ2D February   2018  – April 2024 TUSB1044

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.1
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Custom Alternate Mode
      5. 6.4.5 Linear EQ Configuration
      6. 6.4.6 Adjustable VOD Linear Range and DC Gain
      7. 6.4.7 USB3.1 Modes
    5. 6.5 Programming
      1. 6.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
      2. 6.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
      3. 6.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
    6. 6.6 Register Maps
      1. 6.6.1 TUSB1044 Registers
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 System Examples
      1. 7.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 7.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 7.3.3 DisplayPort Only
      4. 7.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 7.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 7.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 7.3.7 USB3.1 and 4 Lane of Custom Alt Mode
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Linear EQ Configuration

TUSB1044 receiver lanes have controls for receiver equalization for upstream and downstream facing ports. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 6-7 details the gain value for each available combination when TUSB1044 is in GPIO mode. These same options are also available per channel and for upstream and downstream facing ports in I2C mode by updating registers URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL.

Table 6-7 TUSB1044 Receiver Equalization GPIO Control
Downstream Facing Ports using 1100mV linearity settingUpstream Facing Port using 1100mV linearity setting
EQ Setting#DEQ1
pin
Level
DEQ0
pin
Level
EQ GAIN
5GHz
(dB)
EQ GAIN
4.05GHz
(dB)
UEQ1
pin
Level
UEQ0
pin
Level
EQ GAIN
5GHz
(dB)
EQ GAIN
4.05GHz
(dB)
000-2.1-1.400-4.4-3.3
10R00.40R-2.2-1.5
20F1.51.70F0.70.0
3013.03.2010.91.4
4R04.04.1R01.92.4
5RR5.05.2RR3.03.5
6RF5.96.1RF3.84.3
7R16.76.9R14.75.2
8F07.47.7F05.46.0
9FR8.08.3FR6.06.6
10FF8.58.8FF6.57.2
11F19.09.4F17.17.7
12109.49.8107.58.1
131R9.810.31R7.98.6
141F10.110.61F8.39.0
151110.511.0118.69.4