ZHCSSO5A July   2023  – October 2023 TPS7H2140-SEP

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Current and Voltage Conventions
      2. 8.3.2 Accurate Current Sense
      3. 8.3.3 Adjustable Current Limit
      4. 8.3.4 Inductive-Load Switching-Off Clamp
      5. 8.3.5 Fault Detection and Reporting
        1. 8.3.5.1 Diagnostic Enable Function
        2. 8.3.5.2 Multiplexing of Current Sense
        3. 8.3.5.3 Fault Table
        4. 8.3.5.4 FAULT Reporting
      6. 8.3.6 Full Diagnostics
        1. 8.3.6.1 Short-to-GND and Overload Detection
        2. 8.3.6.2 Open-Load Detection
          1. 8.3.6.2.1 Channel On
          2. 8.3.6.2.2 Channel Off
        3. 8.3.6.3 Short-to-Input Detection
        4. 8.3.6.4 Reverse Polarity Detection
        5. 8.3.6.5 Thermal Fault Detection
          1. 8.3.6.5.1 Thermal Shutdown
      7. 8.3.7 Full Protections
        1. 8.3.7.1 UVLO Protection
        2. 8.3.7.2 Loss-of-GND Protection
        3. 8.3.7.3 Protection for Loss of Power Supply
        4. 8.3.7.4 Reverse-Current Protection
        5. 8.3.7.5 MCU I/O Protection
      8. 8.3.8 Parallel Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 Without a GND Network
        2. 9.4.2.2 With a GND Network
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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Inductive-Load Switching-Off Clamp

When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp between drain and source is internally implemented, namely VDS_CLAMP.

Equation 7. V D S _ C L A M P = V I N - V O U T x

During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The total energy is dissipated in the high-side switch (EHSS). Total energy includes the energy of the power supply (EIN) and the energy of the load (ELOAD). If resistance is in series with inductance, some of the load energy is dissipated on the resistance (ER) and the inductor itself (EL).

Equation 8. E H S S = E I N + E L O A D = E I N + E L + E R

When an inductive load switches off, EHSS causes high thermal stressing on the device. The upper limit of the power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition.

GUID-20230306-SS0I-GRKR-XH5P-FB9LMB6N9PPG-low.svg Figure 8-5 Drain-to-Source Clamping Structure
GUID-20230306-SS0I-MQ0Q-NLFJ-J6NWV8VNHLTC-low.svg Figure 8-6 Inductive Load Switching-Off Diagram

From the perspective of the high-side switch, EHSS equals the integration value during the demagnetization period.

Equation 9. E H S S x = 0 t D E C A Y x V D S _ C L A M P   ×   I O U T x ( t )   d t
Equation 10. t D E C A Y x = L R ×   l n R   ×   I O U T ( M A X )   + V O U T   V O U T
Equation 11. E H S S x =   L ×   V I N   + V O U T R 2   ×   R   ×   I O U T ( M A X )     -   V O U T   × l n R   ×   I O U T ( M A X )   + V O U T   V O U T  

When R approximately equals 0, EHSS) can be given simply as:

Equation 12. E H S S x = 1 2   × L ×   I 2 O U T ( M A X )   × V I N   + V O U T V O U T

Figure 8-7 is a waveform of the device driving an inductive load and dissipating 40 mJ of energy across the NMOS pass-element (across IN and OUT1) during the inductive kick-back. The energy was controlled by turning off the channel # 1 at 2.8 (at IOUT1).

The displayed signal definitions are shown in Scope Signals Description

Table 8-1 Scope Signals Description
Channel # Name of the Signal Signal Color
1 VEN1 Blue
2 VIN Red
3 VOUT1 Green
4 IOUT1 Magenta
Math EHSS1 Cyan

The device also optimizes the switching-off slew rate when the clamp is active. This optimization can help the system design by keeping the effects of transient power and EMI to a minimum.

GUID-20230912-SS0I-SDB7-ZDBW-5HRVRLBHWVP4-low.svg Figure 8-7 Inductive Load Switching-Off Waveform of 40mJ
The nominal inductor value use for this waveform is 8mH.

Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry shown in Figure 8-8 to protect the device from repetitive power stressing. TVS is used to achieve the fast decay. See Figure 8-8 for more details.

GUID-20230306-SS0I-KD4W-MJWD-ZDKS0SCLX6QG-low.svg Figure 8-8 Protection With External Circuitry