SLVS530D SEPTEMBER   2005  – October 2015 TPS63700

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Load Disconnect
      3. 7.3.3 Output Overvoltage Protection
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Overtemperature Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft-Start
      2. 7.4.2 PWM Operation
      3. 7.4.3 Power Save Mode Operation
      4. 7.4.4 Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming the Output Voltage: Converter
          1. 8.2.2.1.1 Inductor Selection
        2. 8.2.2.2 Capacitor Selection
          1. 8.2.2.2.1 Input Capacitor
          2. 8.2.2.2.2 Output Capacitors
        3. 8.2.2.3 Stabilizing the Control Loop
          1. 8.2.2.3.1 Feedback Divider
          2. 8.2.2.3.2 Compensation Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

For all switching power supplies the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths, and for the power-ground tracks. The input and output capacitors should be placed as close as possible to the IC. The diode need to be connected closest to the SW pin to minimize parasitic inductance. For low noise operation small bypass capacitors CIN BP and COUT BP in the nF range can be added close to the IC.

The feedback divider should be placed as close as possible to the VREF pin of the IC. Use short traces when laying out the control ground. Figure 18 shows the layout of the EVM board.

10.2 Layout Example

TPS63700 ai_top1_lvs530.gif Figure 16. Layout Considerations, Top View
TPS63700 ai_bot1_lvs530.gif Figure 17. Layout Considerations, Bottom View
TPS63700 layout_lvs530.gif Figure 18. Layout Circuit