SLVS431C june   2002  – September 2015 TPS61131

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Available Output Voltage Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Controller Circuit
      2. 9.3.2 Synchronous Rectifier
      3. 9.3.3 Device Enable
      4. 9.3.4 Undervoltage Lockout
      5. 9.3.5 Soft-Start
      6. 9.3.6 Power Good
      7. 9.3.7 Low Battery Detector Circuit—LBI/LBO
      8. 9.3.8 Low-EMI Switch
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
      2. 9.4.2 LDO
      3. 9.4.3 LDO Enable
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application Circuit for Adjustable Output Voltage Option
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Programming the Output Voltage
            1. 10.2.1.2.1.1 DC-DC Converter
          2. 10.2.1.2.2 LDO
          3. 10.2.1.2.3 Programming the LBI/LBO Threshold Voltage
          4. 10.2.1.2.4 Inductor Selection
          5. 10.2.1.2.5 Capacitor Selection
            1. 10.2.1.2.5.1 Input Capacitor
            2. 10.2.1.2.5.2 Flying Capacitor DC-DC Converter
            3. 10.2.1.2.5.3 Output Capacitor DC-DC Converter
            4. 10.2.1.2.5.4 Small Signal Stability
            5. 10.2.1.2.5.5 Output Capacitor LDO
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Solution for Maximum Output Power
      3. 10.2.3 Low Profile Solution, Maximum Height 1.8 mm
      4. 10.2.4 Single Output Using LDO as Filter
      5. 10.2.5 Dual Input Power Supply Solution
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resource
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage on FB –0.3 3.6 V
Input voltage on SWN –0.3 12 V
Input voltage on SWP –7 7 V
Maximum voltage between SWP and VOUT –12 V
Input voltage on VOUT, LDOIN, LDOOUT, LDOEN, LDOSENSE, PGOOD, LBO, VBAT, LBI, SKIPEN, EN –0.3 7 V
Operating virtual junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage at VBAT 1.8 6.5 V
Operating free air temperature range, TA –40 85 °C
Operating virtual junction temperature, TJ –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS61130, TPS61131, TPS61132 TPS61130 UNIT
PW (TSSOP) RSA (VQFN)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 100.5 33.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35.9 36.3 °C/W
RθJB Junction-to-board thermal resistance 45.4 11 °C/W
ψJT Junction-to-top characterization parameter 2.6 0.5 °C/W
ψJB Junction-to-board characterization parameter 44.8 11 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC-DC STAGE
VI Input voltage range 1.8 6.5 V
VO Adjustable output voltage range (TPS61130) 2.5 5.5 V
Vref Reference voltage 485 500 515 mV
f Oscillator frequency 400 500 600 kHz
ISW Switch current limit VOUT = 3.3 V 1100 1300 1600 mA
Start-up current limit 0.4 x ISW mA
SWN switch on resistance VOUT = 3.3 V 200 350 mΩ
SWP switch on resistance VOUT = 3.3 V 250 500 mΩ
Total accuracy (including line and load regulation) ±3%
DC-DC
quiescent current		 into VBAT IO = 0 mA, VEN = VBAT = 1.8 V,
VOUT = 3.3 V, ENLDO = 0 V		 10 25 μA
into VOUT IO = 0 mA, VEN = VBAT = 1.8 V,
VOUT = 3.3 V, ENLDO = 0 V		 10 25 μA
DC-DC shutdown current VEN= 0 V 0.2 1 μA
LDO STAGE
VI(LDO) Input voltage range 1.8 7 V
VO(LDO) Adjustable output voltage range (TPS61130) 0.9 5.5 V
IO(max) Output current 200 320 mA
LDO short circuit current limit 500 mA
Minimum voltage drop IO = 200 mA 300 mV
Total accuracy (including
line and load regulation)		 IO ≥ 1 mA ±3%
Line regulation LDOIN change from 1.8 V to
2.6 V at 100 mA,
LDOOUT = 1.5 V		 0.6%
Load regulation Load change from 10% to 90%,
LDOIN = 3.3 V		 0.6%
LDO quiescent current LDOIN = 7 V, VBAT = 1.8 V,
EN = VBAT		 20 30 μA
LDO shutdown current LDOEN = 0 V, LDOIN = 7 V 0.1 1 μA
CONTROL STAGE
VIL LBI voltage threshold VLBI voltage decreasing 490 500 510 mV
LBI input hysteresis 10 mV
LBI input current EN = VBAT or GND 0.01 0.1 μA
LBO output low voltage VO = 3.3 V, IOI = 100 μA 0.04 0.4 V
LBO output low current 100 μA
LBO output leakage current VLBO = 7 V 0.01 0.1 μA
VIL EN, SKIPEN input low
voltage		 0.2 × VBAT V
VIH EN, SKIPEN input high
voltage		 0.8 × VBAT V
VIL LDOEN input low voltage 0.2 × VLDOIN V
VIH LDOEN input high voltage 0.8 × VLDOIN V
EN, SKIPEN input current Clamped on GND or VBAT 0.01 0.1 μA
Power-Good threshold VO = 3.3 V 0.9 × Vo 0.92 × Vo 0.95 × Vo V
Power-Good delay 30 μs
Power-Good output low voltage VO = 3.3 V, IOI = 100 μA 0.04 0.4 V
Power-Good output low current 100 μA
Power-Good output leakage current VPG = 7 V 0.01 0.1 μA
Overtemperature protection 140 °C
Overtemperature hysteresis 20 °C

7.6 Typical Characteristics

Table 1. Table of Graphs

SEPIC CONVERTER FIGURE
Maximum output current vs Input voltage (TPS61130) (VO = 3.3 V, 5 V, 2.5 V) Figure 1 Figure 2
Efficiency vs Output current (TPS61130) (VO = 2.5 V, VI = 1.8 V) Figure 3
vs Output current (TPS61132) (VO = 3.3 V, VI = 1.8 V, 3.8 V) Figure 4
vs Output current (TPS61130) (VO = 5 V, VI = 3.6 V, 6 V) Figure 2
vs Input voltage (TPS61132) Figure 5
Output voltage vs Output current (TPS61132) Figure 6
No-load supply current into VBAT vs Input voltage (TPS61132) Figure 7
No-load supply current into VOUT vs Input voltage (TPS61132) Figure 8
LDO
Maximum output current vs Input voltage (VO = 2.5 V, 3.3 V) Figure 9
vs Input voltage (VO = 1.5 V, 1.8 V) Figure 10
Output voltage vs Output current (TPS61131) Figure 11
Dropout voltage vs Output current (TPS61131, TPS61132) Figure 12
Supply current into LDOIN vs LDOIN input voltage (TPS61132) Figure 13
PSRR vs Frequency (TPS61132) Figure 14
TPS61130 TPS61131 TPS61132 icc_v_vi5v_lvs431.gif
Figure 1. TPS61130 Maximum SEPIC Converter Output Current vs Input Voltage
TPS61130 TPS61131 TPS61132 eff_v_io32v_lvs431.gif
Figure 3. TPS61132 SEPIC Converter Efficiency vs Output Current
TPS61130 TPS61131 TPS61132 eff_v_VI_LVS431.gif
Figure 5. TPS61132 SEPIC Converter Efficiency vs Input Voltage
TPS61130 TPS61131 TPS61132 NLVBAT_v_VI_LVS431.gif
Figure 7. TPS61132 No-Load Supply Current Into VBAT vs Input Voltage
TPS61130 TPS61131 TPS61132 ICC_v_VI25v_LVS431.gif
Figure 2. TPS61130 Maximum SEPIC Converter Output Current vs Input Voltage
TPS61130 TPS61131 TPS61132 eff_v_io5v_lvs431.gif
Figure 4. TPS61130 SEPIC Converter Efficiency vs Output Current
TPS61130 TPS61131 TPS61132 vo_v_io_lvs431.gif
Figure 6. TPS61132 SEPIC Converter Output Voltage vs Output Current
TPS61130 TPS61131 TPS61132 nlvout_v_vi_lvs431.gif
Figure 8. TPS61132 No-Load Supply Current Into VOUT vs Input Voltage
TPS61130 TPS61131 TPS61132 ldo_v_vi33v_lvs431.gif
Figure 9. Maximum LDO Output Current vs LDO Input Voltage
TPS61130 TPS61131 TPS61132 ldovo_v_io_lvs431.gif
Figure 11. TPS61131 LDO Output Voltage vs LDO Output Current
TPS61130 TPS61131 TPS61132 io_v_ldoin_lvs431.gif
Figure 13. TPS61132 Supply Current Into LDOIN vs LDOIN Input Voltage
TPS61130 TPS61131 TPS61132 LDO_v_VI15v_LVS431.gif
Figure 10. TPS61130 Maximum LDO Output Current vs LDO Input Voltage
TPS61130 TPS61131 TPS61132 LDOVDO_v__LVS431.gif
Figure 12. LDO Dropout Voltage vs LDO Output Current
TPS61130 TPS61131 TPS61132 PSRR_v_freq_LVS431.gif
Figure 14. TPS61132 PSRR vs Frequency