ZHCSCT5A September   2014  – January 2017 TPS54561-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse-Skipping Eco-mode Control Scheme
      4. 7.3.4  Low-Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjust Undervoltage Lockout
      8. 7.3.8  Soft-Start and Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency
      12. 7.3.12 Synchronization to RT/CLK Pin
      13. 7.3.13 Power Good (PWRGD Pin)
      14. 7.3.14 Overvoltage Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small-Signal Model for Loop Response
      17. 7.3.17 Simplified Small-Signal Model for Peak-Current-Mode Control
      18. 7.3.18 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI = < 4.5 V (Minimum VDD)
      2. 7.4.2 Operation With EN Control
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection (L(O))
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Catch Diode
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Soft-Start Capacitor
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  Undervoltage Lockout Set Point
        10. 8.2.2.10 Output Voltage and Feedback Resistor Selection
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
        13. 8.2.2.13 Power Dissipation Estimate
      3. 8.2.3 Safe Operating Area
      4. 8.2.4 Application Curves
      5. 8.2.5 Inverting Power Supply
      6. 8.2.6 Split-Rail Power Supply
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
      2. 11.2.2 使用 WEBENCH® 工具定制设计方案
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

Layout is a critical portion of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. See Figure 72 for a PCB layout example.

  • To reduce parasitic effects, bypass the VDD pin to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric.
  • Take care to minimize the loop area formed by the bypass capacitor connections, the VDD pin, and the anode of the catch diode. Route the SW pin to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching node, locate the catch diode and output inductor close to the SW pins, and minimize the area of the PCB conductor to prevent excessive capacitive coupling.
  • Tie the GND pin directly to the copper pad under the IC for the exposed thermal pad. Connect this copper pad to internal PCB ground planes using multiple vias directly under the IC.
  • For operation at full-rated load, the top-side ground area must provide adequate heat dissipating area.
  • The RT/CLK pin is sensitive to noise, so locate the RT resistor as close as possible to the IC and route conductors with minimal lengths of trace.
  • Figure 72 shows the approximate placement for the additional external components.
  • It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout, meant as a guideline, demonstrably produces good results.

Boxing in the components in the design of Figure 46, the estimated printed-circuit board area is 1.025 in2 (661 mm2). This area does not include test points or connectors. To further reduce the area, use a two-sided assembly and replace the 0603-sized passives with a smaller-sized equivalent.

Layout Example

TPS54561-Q1 layout_SLVSC60.gif Figure 72. PCB Layout Example