ZHCSCB4C march 2014 – march 2021 TPS3700-Q1
PRODUCTION DATA
In a typical TPS3700-Q1 application, the outputs are connected to a reset or enable input of the processor (such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-specific integrated circuit [ASIC]) or the outputs are connected to the enable input of a voltage regulator (such as a DC-DC or low-dropout regulator [LDO]).
The TPS3700-Q1 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to hold these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to the proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels. The TPS3700-Q1 outputs can be pulled up to 18 V, independent of the device supply voltage. To ensure proper voltage levels, some thought should be given while choosing the pullup resistor values. The pullup resistor value is determined by VOL, sink-current capability, and output-leakage current (Ilkg(OD)). These values are specified in the Section 6.5 table. By using wired-AND logic, OUTA and OUTB can merge into one logic signal.
Table 7-1 and the Section 7.3.1 section describe how the outputs are asserted or de-asserted. See Figure 6-1 for a timing diagram that describes the relationship between threshold voltages and the respective output.