ZHCSTG6A July   2023  – October 2023 TPS25984

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. 说明(续)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power-Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 FET Health Monitoring
      15. 8.3.15 Single Point Failure Mitigation
        1. 8.3.15.1 IMON Pin Single Point Failure
        2. 8.3.15.2 ILIM Pin Single Point Failure
        3. 8.3.15.3 IREF Pin Single Point Failure
        4. 8.3.15.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
      3. 9.1.3 Multiple eFuses, Parallel Connection With PMBus
      4. 9.1.4 Digital Telemetry Using External Microcontroller
    2. 9.2 Typical Application: 12-V, 3.3-kW Power Path Protection in Data Center Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Typical Characteristics

GUID-20230706-SS0I-GQQW-MW9C-DRM4DH9LX76S-low.svgFigure 7-1 ON Resistance Across Temperature
GUID-20230706-SS0I-V3HB-DDJ7-NLPP6WSRRVVG-low.svgFigure 7-3 VIN Undervoltage Thresholds Across Temperature
GUID-20230706-SS0I-L27V-GN43-VNDPNQ1MT1GQ-low.svgFigure 7-5 EN/UVLO Thresholds For FET Turn-off Across Temperature
GUID-20230706-SS0I-FDVW-9PKT-FBJNKWZJT9F7-low.svgFigure 7-7 IREF Charging Current Across Temperature
GUID-20230706-SS0I-ZZ3W-HTRG-0FCVXXHS0D4D-low.svgFigure 7-9 ackup Overcurrent Protection Threshold (Start-up) Accuracy
GUID-20230706-SS0I-RHCH-FL1G-Q6GQRTH3MHDQ-low.svgFigure 7-11 ITIMER Pin Internal Pullup Voltage Across Temperature
GUID-20230706-SS0I-RHVX-FF4F-6MDXKSFJKGZX-low.svgFigure 7-13 ITIMER Pin Discharge Differential Voltage Threshold Across Temperature
GUID-20230706-SS0I-7GJ9-RTNL-WK7JVZ7NKTGG-low.svgFigure 7-15 DVDT Charging Current Across Temperature
GUID-20230706-SS0I-DNWH-7VBL-W7NT4ZVSGMD4-low.svgFigure 7-17 QOD Sink Current Across Temperature
GUID-20230710-SS0I-LWDW-GDCC-NKW4JRSFLHKV-low.svg
Input hot-plugged into 12 V supply
Figure 7-19 Input Hot-plug With Insertion Delay
GUID-20230710-SS0I-ZDFW-XFTV-WMTZZWJWQFGM-low.svg
Input supply held steady, EN/UVLO pin toggled low and high
Figure 7-21 Power Up and Down Sequencing Using EN/UVLO Pin
GUID-20230710-SS0I-HMN9-7GM3-RT1XFNWPKHJN-low.svg
Input supply held steady, EN/UVLO pin toggled from high (above VUVLO(R)) to low (below VSD(F))
Figure 7-23 Power Down Control Using EN/UVLO Pin
GUID-20230710-SS0I-HDTM-DQPR-2KPWQBWFR6V0-low.svg
Input supply held steady, EN/UVLO pin toggled from high (above VUVLO(R)) to intermediate voltage (below VUVLO(F) and above VSD(F)) and held there
Figure 7-25 Power Down Control Using EN/UVLO Pin with Quick Output Discharge (QOD)
GUID-20230713-SS0I-89JG-7SLF-WGWB970CVHDW-low.svg
COUT = 18 mF, CdVdt = 33 nF
Figure 7-27 Inrush Current Control with Capacitive Load
GUID-20230712-SS0I-8PRX-3MSK-N5R7NMXKHNVT-low.svg
Input supply ramped up above 16.6 V.
Figure 7-29 Input Overvoltage Protection Response
GUID-20230710-SS0I-PJMS-KCRG-MVRGHZ3PKPHR-low.svg
IOCP = 55 A, tITIMER = 16 ms, IOUT pulsed above the IOCP threshold for duration shorted than tITIMER without triggering circuit-breaker response.
Figure 7-31 Peak Current Support Using Transient Overcurrent Blanking
GUID-20230710-SS0I-9DF8-FZ34-DZFFPH0CR6CT-low.svg
IOCP = 55 A, Output hard-short to GND while in steady. IOUT rises above 2 × IOCP triggers fast-trip response
Figure 7-33 Short-Circuit Protection Response
GUID-20230706-SS0I-GJC4-Z61G-6S4RQZCFK1JG-low.svgFigure 7-2 VDD Undervoltage Thresholds Across Temperature
GUID-20230706-SS0I-P9KB-S6CZ-KWZZXSHDLCBL-low.svgFigure 7-4 VIN Overvoltage Protection Thresholds Across Temperature
GUID-20230706-SS0I-CNGF-MLN9-CQRBF8SBGDXK-low.svgFigure 7-6 EN/UVLO Based Thresholds for Device Shutdown Across Temperature
GUID-20220929-SS0I-MQFB-N0VH-7BP7PSD2RK4J-low.svgFigure 7-8 IMON Gain Across Load and Temperature
GUID-20230706-SS0I-4FG3-LL5S-PTJFB8X6M6RQ-low.svgFigure 7-10 Backup Overcurrent Protection Threshold (Steady-State) Accuracy
GUID-20230706-SS0I-JPDF-7MZG-DG2NBF32QKPG-low.svgFigure 7-12 ITIMER Pin Discharge Current Across Temperature
GUID-20230706-SS0I-QX2J-S5BC-56XQKK8VWFWS-low.svgFigure 7-14 SWEN Pin Logic Thresholds Across Temperature
GUID-20230706-SS0I-WW7Q-WLVD-7G0NFDGQB4NV-low.svgFigure 7-16 DVDT Gain Across Temperature
GUID-20230718-SS0I-FQZ2-ZRHD-JBSRPL4RBDJN-low.svgFigure 7-18 Junction Temperature vs Load Current (No Air-Flow)
GUID-20230710-SS0I-0DNQ-GLJ5-JDKDSDXKQH4X-low.svg
EN/UVLO pin held high, Input supply ramped up to 12 V
Figure 7-20 Power Up Control Using Input Supply
GUID-20230710-SS0I-1SGT-NG7P-WZDRV89FX0QJ-low.svg
Input supply held steady, EN/UVLO pin toggled from low (below VSD(F)) to high (above VUVLO(R))
Figure 7-22 Power Up Control Using EN/UVLO Pin
GUID-20230710-SS0I-RMRR-ZPLC-RG9DJXN0ZWWV-low.svg
Input supply held steady, EN/UVLO pin toggled from high (above VUVLO(R)) to low (below VSD(F))
Figure 7-24 Power Down Control Using EN/UVLO Pin without engaging Quick Output Discharge (QOD)
GUID-20230710-SS0I-B5H4-FTQ7-VC2Q5VPL4DVP-low.svg
Input supply held steady, EN/UVLO pin held high, SWEN pin toggled low and high
Figure 7-26 Power Up and Down Sequencing Using SWEN Pin
GUID-20230713-SS0I-GGNB-TLPP-D5FJHPLM8JBG-low.svg
COUT = 15.5 mF, ROUT = 0.6 Ω, CdVdt = 33 nF
Figure 7-28 Inrush Current Control with Capacitive and Resistive Load
GUID-20230712-SS0I-VQC3-PSCM-TDQG5B3LGJKP-low.svg
Input supply ramped up above 16.6 V and then ramped down to 12 V.
Figure 7-30 Input Overvoltage Protection Response Followed By Recovery
GUID-20230710-SS0I-770N-QXVG-8GVGXRM6GVLN-low.svg
IOCP = 55 A, tITIMER = 16 ms, IOUT stays above the IOCP threshold persistently to trigger circuit-breaker response.
Figure 7-32 Overcurrent Protection Response (Circuit-Breaker)
GUID-20230710-SS0I-T5QJ-SXL1-NNM68CVCLDSJ-low.svg
Device turned on using EN/UVLO pin with output hard-short to GND. Device limits the current with foldback and then hits thermal shutdown.
Figure 7-34 Power Up into Short-Circuit