ZHCSFW3 November   2016 TPL0401A-10-Q1 , TPL0401B-10-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Voltage Divider Mode
    5. 9.5 Programming
      1. 9.5.1 I2C General Operation and Overview
        1. 9.5.1.1 START and STOP Conditions
        2. 9.5.1.2 Data Validity and Byte Formation
        3. 9.5.1.3 Acknowledge (ACK) and Not Acknowledge (NACK)
        4. 9.5.1.4 Repeated Start
      2. 9.5.2 Programing With I2C
        1. 9.5.2.1 Write Operation
        2. 9.5.2.2 Read Operation
    6. 9.6 Register Maps
      1. 9.6.1 Slave Address
      2. 9.6.2 Register Address
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequence
    2. 11.2 Power-On Reset Requirements
    3. 11.3 I2C Communication After Power Up
    4. 11.4 Wiper Position While Unpowered and After Power Up
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档　
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Power Supply Recommendations

11.1 Power Sequence

Protection diodes limit the voltage compliance at SDA, SCL, terminal H, and terminal W, making it important to power up VDD first before applying any voltage to SDA, SCL, terminal H, and terminal W. The diodes are forward-biasing, meaning VDD can be powered unintentionally if VDD is not powered first. The ideal power-up sequence is VDD, digital inputs, and VW and VH. The order of powering digital inputs, VH and VW does not matter as long as they are powered after VDD.

11.2 Power-On Reset Requirements

In the event of a glitch or data corruption, the TPL0401-10-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

TPL0401A-10-Q1 TPL0401B-10-Q1 pwron01_slis182.gif Figure 22. VDD is Lowered to 0 V and then Ramped Up to VDD

Table 4 specifies the performance of the power-on reset feature for TCA6408A for both types of power-on reset.

Table 4. Recommended Supply Sequencing and Ramp Rates at TA = 25°C(1)

PARAMETER MIN MAX UNIT
tFT Fall rate See Figure 22 0.0001 1000 ms
tRT Rise rate See Figure 22 0.0001 1000 ms
tRR_GND Time to re-ramp (when VDD drops to GND) See Figure 22 1 μs
(1) Not tested. Specified by design.

11.3 I2C Communication After Power Up

In order to ensure a complete device reset after a power up condition, the user must wait 120 µs after power up before initiating communication with the TPL0401x-10-Q1. See Figure 23 for an example waveform.

TPL0401A-10-Q1 TPL0401B-10-Q1 startupwrite_slis182.gif Figure 23. Recommended Start Up Sequence

11.4 Wiper Position While Unpowered and After Power Up

When DPOT is powered off, the impedance of the device is undefined and not known.

Upon power-up, the device returns to 0×40h code because this device does not contain non-volatile memory.