9.1.1 DAC Type

TPIC2040 has seven channels of Actuator. Each channel is assigned to the most suitable DAC engine with a different type respectively. ACT(F/T/Ti) has 12-bit DAC. Upper 8 (MSB sign bit) are converted at a time in 5MHz and LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN, SLED and Load DAC has same DAC types and sampling rate with 312 kHz. All channel except SLED have x6 gain. Table 32 shows configuration of each actuator.

9.1.2 Example of 12-Bit DAC Sampling Rate for FCS/TRK/TLT

The input data is separated in the upper 8bits and the lower 4bits. Upper 8bits (MSB sign 1bit) will be put into 8bit current DAC in every 5 MHz. The lower 4bits will be put into one bit current DAC in sequence from upper to lower bit. This one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25% or 0%, will be summed in 8bit current DAC in every 1.25 MHz. Thus it takes 3.2 µs for all lower 4bits summing to PWM output. As a result, 12-bit data is sampled in every PWM cycle. Example of sampling rate for FCS/TRK/TLT is Figure 44.

Figure 44. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)

9.1.3 Digital Input Coding

The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12bit in two’s complement though some DAC has a low resolution. When 12 bits data is input 8 bits DAC, TPIC2040 recognizes four subordinate position bits (LSB) as 0. To arrange for 12-bit DAC format, DSP should shift 8bit or 10 bit data to an appropriate bit position. The full scale is ±1.0 V and driver gain is set 6. The output voltage (Vout) is given by the following equation:

Equation 1.

Equation 2.

where

• bit[11:0] is the digital input value, range 000000000000b to 111111111111b.

Figure 45. Output Voltage vs DAC Code

9.1.4 Example Timing of Target Control System

TPIC2040 is designed for that meets the requirements updating control data in 400 kHz. The example of control system parameter is listed in Table 34. It takes 0.51 µs for transmit a 16bit data packet to TPIC2040 with 35MHz SCLK. Therefore, DSP can be sent four packets a 400-kHz interval. If SCLK is lower than 28.8MHz, it is required reducing packet quantity under three. For example, Focus/Truck command is updating in every 2.5 µs (400 kHz), and it is able to send another two kind of packet in this same slot. Figure 10 Example DAC control shows the example of the control timing when TPIC2040 is used.

Figure 46. Example DAC Control

9.1.5 Spindle Motor Driver Part

When VSPM is set a positive DAC code then it will be into acceleration mode. IS mode operates then the start-up circuit offers the special start-up pattern sequence to the driver in start-up, and then switches to spin-up mode by detecting the rotor position by BEMF signal from the spindle motor coil.

The spin-down and brake function also be controlled by VSPM DAC value. When it is set the brake command to VSPM, driver goes into active-brake mode, then switch to short-brake mode in slow revolution speed, and then stop automatically. The FG signal is composed from EXOR of three-phase signal, and is output from XFG pin as　shown in Figure 47.

Figure 47. Spindle Operating Sequence

• TI recommends to use down-edge of FG signal for monitoring FG frequency. The FG terminal needs to be pulled up to the appropriate supply voltage by external resistor.
• Short brake mode is asserted after 300 ms of FG signal stays L-level in deceleration.
• The FG output is set to H-level in sleep mode in order to reduce sleep mode current.
• This value is the nominal number of using motor with 16-poles.
• First of all, power supply voltage of P5V must be supplied before any signals input.

9.1.5.1 Spindle PWM Control

The output PWM duty of Spindle is controlled by DAC code (VSPM). The gain in acceleration setting is always six times. However, the maximum output is restricted to P5V_SPM voltage. A dead band which output = 0 exists in the width of plus or minus 0x52 focusing on zero.

Figure 48. Spindle PWM Control

9.1.5.2 Auto Short Brake Function

TPIC2040 provides auto short brake function which is selecting brake mode automatically by motor speed.

Auto Short Brake is the intelligent brake function that includes two modes: short brake and active brake.

When VSPM value is controlled more than equivalent 75% duty brake, deceleration is done by short brake under the rotation speed is over 3000 rpm. After deceleration, driver goes into Active-brake mode automatically by internal logic circuit under rotation speed is lower 2000 rpm. This function enables low power consumption and silent during braking.

Table 35. Brake Mode

VSPM[11:0]	ROTATION SPEED (RPM)
	ABOUT 0 TO 2000	ABOUT 3000
0x000 - 0xFAE	2-phase short brake	2-phase short brake
0xFAE - 0xA00	Active brake	Active brake
0xA00 - 0x800	Active brake	3-phase short brake

Figure 49. Brake Mode Selections

This value is the nominal number of using motor with 16-poles motor.

9.1.5.3 Spindle Low-Speed Mode

LS mode is the low rotation mode which made the maximum 25% duty. When using SPM_LSMODE = 1, brake mode is always short brake. Figure 50 shows the output duty of LS mode.

Figure 50. Spindle PWM Control (Low-Speed Mode)

9.1.6 Sled Driver Part

9.1.6.1 Sled Channel Input versus Output PWM Duty

The Sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feed back. The maximum output is restricted to 440 mA at 0x7FF and 0x800. A dead band which output = 0 exists in the width of plus or minus focusing on zero.

Figure 51. Sled Output Current

• Both outputs of SLED1/2 are L when input code is in dead band.

9.1.6.2 Sled End Detect Function

This device has the function of end position detection for Sled. By this function aim to eliminate the position switch at PUH inner. When this function is enabled, internal logic will detect the sled out zero-cross point and at that time, internal BEMF detect circuit measures the BEMF level of stepping motor. There are six threshold levels. If BEMF is lower than selected threshold, device recognizes motor at stop and ENDDET bit to 1. ENDDET bit will be cleared at the BEMF voltage exceed threshold again.

Figure 52. Timing of Sled End Detection

• In order to perform high-precision detection, the sled motor needs to generate higher BEMF voltage. BEMF level depends on the stepping motor characteristic and its speed.
• BEMF detection level is selectable 22, 46, 82, 105, 125, 145 mV.

If the drive speed changes, the timing which BEMF voltage generates will also change. In TPIC2040, detection window can be adjusted to the optimal value by setting EDET_DELAY parameter. Delay time from the point which polarity reverses and width of detection window are adjustable with EDET_DELAY.

Figure 53. Timing of End Detection Window

9.1.7 Load Driver Part

Load driver outputs the voltage with voltage feedback corresponding to the input DAC value. This channel has power voltage compensation thus it is suit for Slot-in type load control. This channel becomes active exclusively to other actuator channels. Load driver is shared with the TRK driver.

Figure 54. Load Output Duty

• Output voltage is controlled by PWM
• Both LOAD+ and LOAD– are connected to PGND through the internal clamp diode respectively.

9.1.8 Focus/Track/Tilt Driver Part

Figure 55. FCS/TRK/TLT Output Duty

9.1.9 9-V LDO

TPIC2040 built in function a pre-driver for LDO. The required voltage beyond 1.2 V can be outputted on N-channel FET by choosing external resistance. Arbitrary current can be supplied by selecting the external N-channel FET according to required current capacity. LIN3VG output (= N-channel FET gate control) is controlled to Feedback voltage LINFB is set as 1.215 V. The 22-nF capacitor for phase compensation is certainly installed. And the division resistance for FB is chosen so that it may become less than 3K in total. The example of external components shows Figure 56. The accuracy of output voltage depends for tolerance of resistance.

When not using LDO, it should be open LIN3VG and LINFB should be connected to 3.3 V with LIN3P3_DIS = 1.

Figure 56. Example Circuit of 3.3-V LDO

9.1.10 Monitor Signal on GPOUT

Able to output a specific signal to GPOUT pin. In order to output a signal, set a signal from REG6F by enabling first and then enable GPOUT_ENA. When two or more signals are set for GPOUT, an output is as logical sum.

It is required to set both LIN3P3_DIS and GPOUT_ENA to 1.

Table 37. Pin Connection When Specific Function is not Applied

9.2.1 Design Requirements

To begin the design process, determine the following:

1. Motor configuration: The user can use all motor channels or some of them.
2. Power up devices with a 5-V supply.

9.2.2 Detailed Design Procedure

After power up on 5-V supply, the following values may be written to the following registers to enable motors.

1. Set WRITE_ENABLE = 1 on REG76 via SPI.
2. Set XSLEEP = 1 at REG70
3. Enable motor channel by ENA_XXX bits on REG70
4. Change the DAC settings for each motor in REG01-0B. Then, output channels will start driving load.

9.2.3 Application Curves

Figure 58. DAC Code vs Duty Cycle for FCS Outputs

Figure 59. DAC Code vs Duty Cycle for TLT Outputs