6.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, watchdog timer and the RSTCTRL Register of the PLL controller; that is, a hard reset or a soft reset. By default, these resets will be hard resets. The Reset Configuration Register (RSTCFG) is shown in Figure 6-11 and described in Table 6-17.
Figure 6-11 Reset Configuration Register (RSTCFG)
Reserved |
PLLCTLRST
TYPE |
RESETTYPE |
Reserved |
WDTYPE[N(1)] |
R-0 |
R/W-0(2) |
R/W-02 |
R-0 |
R/W-02 |
Legend: R = Read only; R/W = Read/Write; -n = value after reset |
(1) Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual).
(2) Writes are conditional based on valid key. For details, see
Section 6.5.2.7.
Table 6-17 Reset Configuration Register (RSTCFG) Field Descriptions
BIT |
FIELD |
DESCRIPTION |
31-14 |
Reserved |
Reserved. |
13 |
PLLCTLRSTTYPE |
PLL controller initiates a software-driven reset of type:
- 0 = Hard reset (default)
- 1 = Soft reset
|
12 |
RESETTYPE |
RESET initiates a reset of type:
- 0 = Hard Reset (default)
- 1 = Soft Reset
|
11-4 |
Reserved |
Reserved. |
3 |
WDTYPE3 |
Watchdog timer [N] initiates a reset of type:
- 0 = Hard Reset (default)
- 1 = Soft Reset
|
2 |
WDTYPE2 |
Watchdog timer [N] initiates a reset of type:
- 0 = Hard Reset (default)
- 1 = Soft Reset
|
1 |
WDTYPE1 |
Watchdog timer [N] initiates a reset of type:
- 0 = Hard Reset (default)
- 1 = Soft Reset
|
0 |
WDTYPE0 |
Watchdog timer [N] initiates a reset of type:
- 0 = Hard Reset (default)
- 1 = Soft Reset
|