ZHCSH92D December   2017  – June 2022 TLIN2022-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC
    4. 6.4 Thermal Information
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics (1)
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
      1.      Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  LIN (Local Interconnect Network) Bus
        1. 7.3.1.1 LIN Transmitter Characteristics
        2. 7.3.1.2 LIN Receiver Characteristics
          1. 7.3.1.2.1 Termination
      2. 7.3.2  TXD (Transmit Input and Output)
      3. 7.3.3  RXD (Receive Output)
      4. 7.3.4  VSUP (Supply Voltage)
      5. 7.3.5  GND (Ground)
      6. 7.3.6  EN (Enable Input)
      7. 7.3.7  Protection Features
      8. 7.3.8  TXD Dominant Time Out (DTO)
      9. 7.3.9  Bus Stuck Dominant System Fault: False Wake Up Lockout
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Under Voltage on VSUP
      12. 7.3.12 Unpowered Device and LIN Bus
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Wake Up Events
        1. 7.4.4.1 Wake Up Request (RXD)
        2. 7.4.4.2 Mode Transitions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Normal Mode Application Note
        2. 8.2.2.2 Standby Mode Application Note
        3. 8.2.2.3 TXD Dominant State Timeout Application Note
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

  • Pin 1, 4 (RXD1/2): The pin is an open drain outputs and require an external pull-up resistor in the range of 1 kΩ and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated pull-up, an external resistor should be placed between RXD and the regulated voltage supply for the microprocessor.
  • Pin 2, 5 (EN1/2): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pinto limit current on the digital lines in the event of an over voltage fault.
  • Pin 6 (NC): Not Connected.
  • Pin 3, 7 (TXD1/2): The TXD pins are the transmitter input signals to the device from the processor. A series resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to ground can be placed close to the input pin of the device to filter noise.
  • Pin 8 (GND): This is the ground connection for the device. This pin should be tied to the ground plane through a short trace with the use of two vias to limit total return inductance.
  • Pin 9, 13 (LIN1/2): This pin connects to the LIN bus. For responder applications, a 220 pF capacitor to ground is implemented. For commander applications and additional series resistor, a blocking diode should be placed between the LIN pin and the VSUP pin. See Figure 8-1.
  • Pin 10 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close to the device as possible.
  • Pin 11, 12 and 14 (NC): Not Connected.
Note:

All ground and power connections should be made as short as possible and use at least two vias to minimize the total loop inductance.