9.2.2.1 Setting Maximum Channel Current

The maximum output current per channel is programmed by a single resistor, R_(IREF), which is placed between the IREF pin and the GND pin. The voltage on the IREF pin is set by an internal band gap V_(IREF) with a typical value of 1.24 V. The maximum channel current is equivalent to the current flowing through R_(IREF) multiplied by a factor of 31.5. The maximum output current can be calculated by Equation 7.

Equation 7.

where

• V_(IREF) = 1.24 V
• R_(IREF) = User-selected external resistor.

The value of I_max must be set between 5 mA and 60 mA. The output current may be unstable if I_max is set lower than 5 mA. Output currents lower than 5 mA can be achieved by setting I_max to 5 mA or higher and then using dot correction.

Figure 1 shows the maximum output current I_O versus R_(IREF). R_(IREF) is the value of the resistor between IREF terminal to GND, and I_O is the constant output current of OUT0 to OUT15. A variable power supply may be connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum output current per channel is 31.5 times the current flowing out of the IREF pin.

9.2.2.2 Power Dissipation Calculation

The device power dissipation must be below the power dissipation rate of the device package to ensure correct operation. Equation 8 calculates the power dissipation of device.

Equation 8.

where

• V_CC: device supply voltage
• I_CC: device supply current
• V_OUT: TLC5941-Q1 OUTn voltage when driving LED current
• I_MAX: LED current adjusted by R_(IREF) resistor
• DC_n: maximum dot correction value for OUTn
• N: number of OUTn driving LED at the same time
• d_PWM: duty cycle defined by BLANK pin or GS PWM value

9.2.2.3 Setting Dot Correction

The TLC5941-Q1 device has the capability to fine-adjust the output current of each channel (OUT0 to OUT15) independently which is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current I_max. The TEST pin must be connected to V_CC to ensure proper operation of the dot correction circuitry. Equation 9 calculates the output current for each output n.

Equation 9.

where

• I_max = the maximum programmable output current for each output.
• DCn = the programmed dot correction value for output n (DCn = 0 to 63)
• n = 0 to 15

Figure 19 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1 and so on. The DC 15.5 in Figure 19 stands for the 5^th-most significant bit for output 15.

Figure 19. Dot Correction Data Packet Format

When the MODE pin is set to V_CC, the TLC5941-Q1 device enters the dot correction data input mode. The length of input shift register becomes 96bits. After all serial data are shifted in, the TLC5941-Q1 device writes the data in the input shift register to DC register when the XLAT pin is high, and holds the data in the DC register when the XLAT pin is low. The DC register is a level triggered latch of the XLAT signal. Because the XLAT pin is a level-triggered signal, SCLK and SIN must not be changed while the XLAT pin is high. After the XLAT pin goes low, data in the DC register is latched and does not change. The BLANK signal does not need to be high to latch in new data. When the XLAT pin goes high, the new dot-correction data immediately becomes valid and changes the output currents if the BLANK pin is low. the XLAT pin has setup time (t_su1) and hold time (t_h1) to SCLK as shown in Figure 12.

To input data into the dot correction register, the MODE pin must be set to V_CC. The internal input shift register is then set to 96-bit width. After all serial data are clocked in, a rising edge of the XLAT pin is used to latch the data into the dot correction register. Figure 20 shows the DC-data input-timing chart.

Figure 20. Dot-Correction Data Input-Timing Chart

9.2.2.4 Setting Grayscale

The TLC5941-Q1 device can adjust the brightness of each channel, OUTn, using a PWM control scheme. The use of 12 bits per channel results in 4096 different brightness steps, from 0% to 100% brightness. Equation 10 calculates the brightness level for each output n.

Equation 10.

where

• GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
• n = 0 to 15
• Grayscale data for all OUTn

The input shift register enters grayscale data into the grayscale register for all channels simultaneously. The complete grayscale data format consists of 16 × 12 bit words, which forms a 192-bit wide data packet (see Figure 21). The data packet must be clocked in with the MSB first.

Figure 21. Grayscale Data Packet Format

When the MODE pin is set to GND, the TLC5941-Q1 device enters the grayscale data input mode. The device switches the input shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into the grayscale register (see Figure 22). New grayscale data immediately becomes valid at the rising edge of the XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is high. The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register is replaced with status information data (SID) after updating the grayscale register.

Figure 22. Grayscale Data Input Timing Chart

9.2.2.5 Serial Data Transfer Rate

Figure 18 shows a cascading connection of n TLC5941-Q1 devices connected to a controller, building a basic module of an LED display system. The TLC5941-Q1 device has no limit to the maximum number of ICs that can be cascaded. The maximum number of cascading TLC5941-Q1 devices depends on the application system and is in the range of 40 devices. Equation 11 calculates the minimum frequency needed:

Equation 11.

where

• f_(GSCLK): minimum frequency needed for GSCLK
• f_(SCLK): minimum frequency needed for SCLK and SIN
• f_(update): update rate of whole cascading system
• n: number cascaded of TLC5941-Q1 device