ZHCSP69E August   2009  – May 2022 TCA9535

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Tolerant I/O Ports
      2. 7.3.2 Hardware Address Pins
      3. 7.3.3 Interrupt ( INT) Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Powered-Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 Bus Transactions
          1. 7.5.1.1.1 Writes
          2. 7.5.1.1.2 Reads
      2. 7.5.2 Device Address
      3. 7.5.3 Control Register and Command Byte
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 8.2.1.2 Minimizing ICC When I/O is Used to Control LED
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-BCB5CE92-8BBB-4576-9FCB-01BB92DBCC21-low.gifFigure 5-1 DB, PW (TSSOP) Package
24-Pin (Top View)
GUID-BA4DC73C-1EAE-478F-BF66-5D62F97A9237-low.gif
The exposed center pad, if used, must be connected as a secondary ground or left electrically open.
Figure 5-2 RTW (WQFN), RGE (VQFN) Package
24-Pin (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DB, PW RTW, RGE
A0 21 18 Input Address input 0. Connect directly to VCC or ground
A1 2 23 Input Address input 1. Connect directly to VCC or ground
A2 3 24 Input Address input 2. Connect directly to VCC or ground
GND 12 9 — Ground
INT 1 22 Output Interrupt output. Connect to VCC through an external pull-up resistor
P00(1) 4 1 I/O P-port I/O. Push-pull design structure. At power on, P00 is configured as an input
P01(1) 5 2 I/O P-port I/O. Push-pull design structure. At power on, P01 is configured as an input
P02(1) 6 3 I/O P-port I/O. Push-pull design structure. At power on, P02 is configured as an input
P03(1) 7 4 I/O P-port I/O. Push-pull design structure. At power on, P03 is configured as an input
P04(1) 8 5 I/O P-port I/O. Push-pull design structure. At power on, P04 is configured as an input
P05(1) 9 6 I/O P-port I/O. Push-pull design structure. At power on, P05 is configured as an input
P06(1) 10 7 I/O P-port I/O. Push-pull design structure. At power on, P06 is configured as an input
P07(1) 11 8 I/O P-port I/O. Push-pull design structure. At power on, P07 is configured as an input
P10(1) 13 10 I/O P-port I/O. Push-pull design structure. At power on, P10 is configured as an input
P11(1) 14 11 I/O P-port I/O. Push-pull design structure. At power on, P11 is configured as an input
P12(1) 15 12 I/O P-port I/O. Push-pull design structure. At power on, P12 is configured as an input
P13(1) 16 13 I/O P-port I/O. Push-pull design structure. At power on, P13 is configured as an input
P14(1) 17 14 I/O P-port I/O. Push-pull design structure. At power on, P14 is configured as an input
P15(1) 18 15 I/O P-port I/O. Push-pull design structure. At power on, P15 is configured as an input
P16(1) 19 16 I/O P-port I/O. Push-pull design structure. At power on, P16 is configured as an input
P17(1) 20 17 I/O P-port I/O. Push-pull design structure. At power on, P17 is configured as an input
SCL 22 19 Input Serial clock bus. Connect to VCC through a pull-up resistor
SDA 23 20 Input Serial data bus. Connect to VCC through a pull-up resistor
VCC 24 21 — Supply voltage
(1) If port is unused, it must be tied to either VCC or GND through a resistor of moderate value (about 10 kΩ)