ZHCS275D July   2010  – January 2023 TCA6424A

PRODUCTION DATA  

  1. 1 特性
  2. 2 说明
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Translation
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 I2C Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Address
    5. 8.5 Programming
      1. 8.5.1 Power-On Reset
      2. 8.5.2 Reset Input ( RESET)
      3. 8.5.3 Interrupt Output ( INT)
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Writes
        2. 8.5.4.2 Reads
    6. 8.6 Register Maps
      1. 8.6.1 Control Register and Command Byte
      2. 8.6.2 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Detailed Design Procedure
        1. 9.1.1.1 Minimizing ICC When I/Os Control LEDs
    2. 9.2 Power Supply Recommendation
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 支持资源
    3. 10.3 商标
    4. 10.4 静电放电警告
    5. 10.5 术语表
      1.      Mechanical, Packaging, and Orderable Information

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9.2 Power Supply Recommendation

In the event of a glitch or data corruption, TCA6424A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

Ramping up the device VCCP before VCCI is recommended to prevent SDA from potentially being stuck LOW.

The two types of power-on reset are shown in #SCPS0691 and #SCPS0692.

GUID-0998D2DD-9706-4414-8D06-7DD22EF0C064-low.gifFigure 9-4 VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
GUID-1DA46EF6-766D-4872-AD2B-9DB35C78F1FA-low.gifFigure 9-5 VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 9-1 specifies the performance of the power-on reset feature for TCA6424A for both types of power-on reset.

Table 9-1 Recommended Supply Sequencing and Rates#SCPS139781
PARAMETERMINTYPMAXUNIT
tVCC_FTFall rateSee #SCPS06911100ms
tVCC_RTRise rateSee #SCPS06910.01100ms
tVCC_TRR_GNDTime to re-ramp (when VCC drops to GND)See #SCPS069140μs
tVCC_TRR_POR50Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)See #SCPS069240μs
VCC_GHLevel that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μsSee #SCPS06931.2V
tVCC_GWGlitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCxSee #SCPS069310μs
VPORFVoltage trip point of POR on falling VCC0.7671.144V
VPORRVoltage trip point of POR on rising VCC1.0331.428V
(1) TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. #SCPS0693 and Table 9-1 provide more information on how to measure these specifications.

GUID-844268C7-14A3-4BD9-94C9-457127414BDC-low.gifFigure 9-6 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to the default states. The value of VPOR differs based on the VCC being lowered to or from 0. #SCPS0694 and Table 9-1 provide more details on this specification.

GUID-EE0149BA-FEBC-4549-8D5F-E65B002A50E4-low.gifFigure 9-7 VPOR