ZHCSRH9E April   2009  – January 2023 TCA6408A

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Translation
      2. 8.3.2 I/O Port
      3. 8.3.3 Interrupt Output ( INT)
      4. 8.3.4 Reset Input ( RESET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. 8.5.2.1 Writes
        2. 8.5.2.2 Reads
    6. 8.6 Register Map
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Minimizing ICC When I/O is Used to Control LEDs
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
      1.      Mechanical, Packaging, and Orderable Information

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6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see GUID-E45F0989-0746-490A-AAB5-352E4279EB6C.html#SCPS133IMG6684)
STANDARD MODE
I2C BUS		FAST MODE
I2C BUS		UNIT
MINMAXMINMAX
fsclI2C clock frequency01000400kHz
tschI2C clock high time40.6μs
tsclI2C clock low time4.71.3μs
tspI2C spike time050050ns
tsdsI2C serial data setup time250100ns
tsdhI2C serial data hold time00ns
ticrI2C input rise time100020 + 0.1Cb300ns
ticfI2C input fall time30020 + 0.1Cb300ns
tocfI2C output fall time, 10-pF to 400-pF bus30020 + 0.1Cb300μs
tbufI2C bus free time between Stop and Start4.71.3μs
tstsI2C Start or repeater Start condition setup time4.70.6μs
tsthI2C Start or repeater Start condition hold time40.6μs
tspsI2C Stop condition setup time40.6μs
tvd(data)Valid data time, SCL low to SDA output valid11μs
tvd(ack)Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low11μs