ZHCSFG1B January   2016  – February 2017 SN75LVPE802

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
      1. 7.8.1 Jitter and VOD results: Case 1 at 6 Gbps
      2. 7.8.2 Jitter and VOD Results: Case 2 at 3 Gbps
      3. 7.8.3 Jitter and VOD Results: Case 3 at 1.5 Gbps
      4. 7.8.4 Jitter and VOD Results: Case 4 at 8 Gbps
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  SATA Express
      2. 8.3.2  Receiver Termination
      3. 8.3.3  Receiver Internal Bias
      4. 8.3.4  Input Equalization
      5. 8.3.5  OOB/Squelch
      6. 8.3.6  Auto Low Power
      7. 8.3.7  Transmitter Output Signal
      8. 8.3.8  Transmitter Common Mode
      9. 8.3.9  De-Emphasis
      10. 8.3.10 Transmitter Termination
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical SATA Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Equalization Configuration
      3. 9.2.3 De-emphasis Configuration
      4. 9.2.4 Application Curves
        1. 9.2.4.1 SN75LVPE802 Equalization Settings for Various Input Trace Length
        2. 9.2.4.2 SN75LVCP802 De-emphasis Settings For various Output Trace Lengths
    3. 9.3 SATA Express Applications
      1. 9.3.1 Detailed Design Procedure
      2. 9.3.2 PCIe Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RTJ|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply Voltage Range(2), VCC –0.5 4 V
Voltage Range Differential I/O –0.5 4 V
Control I/O –0.5 VCC + 0.5 V
Continuous power dissipation See Thermal Information
Storage temperature, Tstg 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±10000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
Machine model(3) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Tested in accordance with JEDEC Standard 22, Test Method A115-A

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply Voltage 3 3.3 3.6 V
C(coupling) Coupling Capacitor 12 nF
TA Operating free-air temperature 0 85 °C

7.4 Thermal Information

THERMAL METRIC(1) SN75LVPE802 UNIT
RTJ (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 38 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 40 °C/W
RθJB Junction-to-board thermal resistance 10 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 0.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 15.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Power dissipation in active mode DEWX = EN = VCC, EQX = DEX = NC, K28.5 pattern at 6 Gbps, VID = 700 mVpp 188 205 mW
PSD Power dissipation in standby mode EN = 0 V, DEWX = EQX = DEX = NC, K28.5 pattern at 6 Gbps, VID = 700 mVpp 4 mW
ICC Active mode supply current EN = 3.3 V, DEWX = EQX = DEX = NC, K28.5 pattern at 6 Gbps, VID = 700 mVpp 57 62 mA
ICC(STDBY) Standby mode supply current EN = 0 V 1 mA
Maximum data rate 8 Gbps
OOB
V(OOB) Input OOB threshold F = 750 MHz 50 78 150 mVpp
DVdiff(OOB) OOB differential delta 25 mV
DVCM(OOB) OOB common-mode delta 50 mV
CONTROL LOGIC
VIH High-level input voltage For all control pins 1.4 V
VIL Low-level input voltage 0.5 V
VIN(HYS) Input hysteresis 115 mV
IIH High-level input current EQx, DEx = VCC 30 µA
EN, DEWx = VCC 1 µA
IIL Low-level input current EQx, DEx = GND –30 µA
EN, DEWx = GND –10 µA
RECEIVER AC/DC
Z(DIFFRX) Differential-Input Impedance 85 100 115 Ω
Z(SERX) Single-Ended Input Impedance 40 Ω
VCM(RX) Common-mode voltage 1.8 V
RL(DiffRX) Differential mode return Loss (RL) f = 150 MHz – 300 MHz 22 28 dB
f = 300 MHz – 600 MHz 14 17 dB
f = 600 MHz – 1.2 GHz 10 12 dB
f = 1.2 GHz – 2.4 GHz 8 9 dB
f = 2.4 GHz – 3 GHz 7 9 dB
f = 3 GHz – 5 GHz 6 8 dB
RX(DiffRLSlope) Differential mode RL slope f = 300 MHz – 6 GHz 14 dB/dec
RL(CMRX) Common mode return loss f = 150 MHz – 300 MHz 9 10 dB
f = 300 MHz – 600 MHz 14 17 dB
f = 600 MHz – 1.2 GHz 15 23 dB
f = 1.2 GHz – 2.4 GHz 13 16 dB
f = 2.4 GHz – 3 GHz 10 12 dB
f = 3 GHz – 5 GHz 4 6 dB
V(diffRX) Differential input voltage PP f = 1.5 GHz and 3 GHz 120 1600 mVppd
IB(RX) Impedance Balance f = 150 MHz – 300 MHz 30 41 dB
f = 300 MHz – 600 MHz 30 38 dB
f = 600 MHz – 1.2 GHz 20 32 dB
f = 1.2 GHz – 2.4 GHz 10 26 dB
f = 2.4 GHz – 3 GHz 10 25 dB
f = 3 GHz – 5 GHz 4 20 dB
f = 5 GHz – 6.5 GHz 4 17 dB
TRANSMITTER AC/DC
Z(diffTX) Pair differential impedance 85 100 122 Ω
Z(SETX) Single-Ended input Impedance 40 Ω
V(TXtrans) Sequencing transient voltage Transient voltages on the serial data bus during power sequencing (lab load) –1.2 1.2 V
RL(DiffTX) Diff Mode return Loss f = 150 MHz – 300 MHz 19 25 dB
f = 300 MHz – 600 MHz 17 19 dB
f = 600 MHz – 1.2 GHz 11 14 dB
f = 1.2 GHz – 2.4 GHz 8 10 dB
f = 2.4 GHz – 3 GHz 8 10 dB
f = 3 GHz – 5 GHz 8 10 dB
TX(DiffRLSlope) Differential-mode RL slope f = 300 MHz to 3 GHz 14 dB/dec
RL(CMTX) Common Mode return Loss f = 150 MHz – 300 MHz 16 20 dB
f = 300 MHz – 600 MHz 15 19 dB
f = 600 MHz – 1.2 GHz 14 17 dB
f = 1.2 GHz – 2.4 GHz 10 12 dB
f = 2.4 GHz – 3 GHz 9 11 dB
f = 3 GHz – 5 GHz 6 7 dB
I(BTX) Impedance Balance f = 150 MHz – 300 MHz 30 41 dB
f = 300 MHz – 600 MHz 30 38 dB
f = 600 MHz – 1.2 GHz 20 33 dB
f = 1.2 GHz – 2.4 GHz 10 24 dB
f = 2.4 MHz – 3 GHz 10 26 dB
f = 3 GHz – 5 GHz 4 22 dB
f = 5 GHz – 6.5 GHz 4 21 dB
DE Output de-emphasis
(relative to transition bit)		 DE1 0r DE2 = 0 0 dB
DE1 0r DE2 = 1 –2 dB
DE1 0r DE2 = NC –4 dB
Diff(VppTX_DE) Differential output-voltage swing dc level DE1 0r DE2 = 0 550 mV
DE1 0r DE2 = 1 830 mV
DE1 0r DE2 = NC 630 mV
V(CMAC_TX) TX AC CM Voltage At 1.5 GHz 20 50 mVppd
At 3 GHz 12 26 dBmV (rms)
At 6 GHz 13 30 dBmV (rms)
V(CMTX) Common-Mode Voltage 1.8 V
TX(R/FImb) TX rise-fall imbalance At 3 GHz 6% 20% V
TX(AmpImb) TX amplitude imbalance 2% 10% V

7.6 Timing Requirements

MIN NOM MAX UNIT
DEVICE PARAMETERS
Auto low-power entry time Electrical idle at input (see Figure 24) 80 105 130 ps
Auto low-power exit time After first signal activity (see Figure 24) 42 50 ps
TRANSMITTER AC/DC
tDE Input OOB threshold DEW1 or DEW2 = 0 94 ps
DEW1 or DEW2 = 1 215 ps
OUT-OF-BAND (OOB)
tOOB1 OOB mode enter See Figure 23 3 5 ns
tOOB2 OOB mode exit 3 5 ns

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE PARAMETERS
tPDelay Propagation delay Measured using K28.5 pattern
(see Figure 1)		 323 400 ps
tENB Device enable time EN 0 → 1 5 µs
tDIS Device disable time EN 1 → 0 2 µs
RECEIVER AC/DC
t20-80RX Rise/fall time Rise times and fall times measured between 20% and 80% of the signal. SATA 6-Gbps speed measured 1 in, (2.5 cm) from device pin. 62 75 ps
tSKEWRX Differential skew Difference between the single-ended midpoint of the RX+ signal rising or falling edge, and the single-ended midpoint of the RX– signal falling or rising edge. 30 ps
TRANSMITTER AC/DC
t20-80TX Rise/fall time Rise times and fall times measured between 20% and 80% of the signal. At 6 Gbps under no load conditions. 42 55 75 ps
tSKEWTX Differential skew Difference between the single-ended midpoint of the TX+ signal rising or falling edge, and the single-ended midpoint of the TX– signal falling or rising edge. 6 20 ps
TRANSMITTER JITTER
DJTX Deterministic jitter (1) at CP in VID = 500 mVpp, UI = 333 ps, K28.5 control character 0.06 5 UIp-p
RJTX Residual Random jitter(1) VID = 500 mVpp, UI = 333 ps, K28.7 control character 0.01 5 ps-rms
DJTX Deterministic jitter (1) at CP in VID = 500 mVpp, UI = 167 ps, K28.5 control character 0.08 0.16 UIp-p
RJTX Residual random jitter (1) VID = 500 mVpp, UI = 167 ps, K28.7 control character 0.09 2 ps-rms
DJTX Deterministic jitter (1) at CP in VID = 500 mVpp, UI = 125 ps, K28.5 control character 0.1 0.2 UIp-p
RJTX Residual random jitter(1) VID = 500 mVpp, UI = 125 ps, K28.7 control character 0.3 1.5 ps-rms
(1) (1) TJ = (14.1 x RJSD + DJ), where RJSD is one standard deviation value
SN75LVPE802 Figure1_PropagationDelayTimingDiagr.gif Figure 1. Propagation Delay Timing Diagram

7.8 Typical Characteristics

Input signal characteristics:

  • Data rate = 8 Gbps 6 bps, 3 Gbps, 1.5 Gbps
  • Amplitude = 500 mVpp
  • o Data pattern = K28.5

SN75LVPE802 device setup:

  • Temperature = 25°C
  • Voltage = 3.3 V
  • De-emphasis duration = 117 ps (short)
  • Equalization and de-emphasis set to optimize performance at 6 Gbps

SN75LVPE802 Figure_6_2_Performance_Curve_Measur.gif Figure 2. Performance Curve Measurement Setup
SN75LVPE802 Figure_6_3_Jitter_Measurement_Test_.gif Figure 3. Jitter Measurement Test Condition

7.8.1 Jitter and VOD results: Case 1 at 6 Gbps

SN75LVPE802 Figure_6_4_Test_Point_1.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
29 3.3 1.88 412.4 159.2 350.52
Figure 4. Test Point 1
SN75LVPE802 Figure_6_6_Test_Point_3.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
42 15.9 1.91 788.8 141.3 623.02
Figure 6. Test Point 3
SN75LVPE802 Figure_6_8_Test_Point_4_Without_LVP.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
56.7 29.8 2 165.4 101 13.24
Figure 8. Test Point 4 Without LVPE802
SN75LVPE802 Figure_6_5_Test_Point_2.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
91.8 65.4 1.93 240 28.9 81.24
Figure 5. Test Point 2
SN75LVPE802 Figure_6_7_Test_Point_4_With_LVPE80.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
39 12.7 1.92 557.1 149.7 459.62
Figure 7. Test Point 4 With LVPE802

7.8.2 Jitter and VOD Results: Case 2 at 3 Gbps

SN75LVPE802 Figure_6_9_Test_Point_1.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
29.7 3.8 1.89 430.9 326 392.84
Figure 9. Test Point 1
SN75LVPE802 Figure_6_11_Test_Point_3.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
39.6 12.8 1.96 714.5 321 611.62
Figure 11. Test Point 3
SN75LVPE802 Figure_6_13_Test_Point_4_Without_LV.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV
128.6 101.8 1.96 258.8 118 122.26
Figure 13. Test Point 4 Without LVPE802
SN75LVPE802 Figure_6_10_Test_Point_2.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
72.7 46.8 1.89 314.9 237 222.36
Figure 10. Test Point 2
SN75LVPE802 Figure_6_12_Test_Point_4_With_LVPE8.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
47.9 20.3 1.99 615.3 305.0 463.42
Figure 12. Test Point 4 With LVPE802

7.8.3 Jitter and VOD Results: Case 3 at 1.5 Gbps

SN75LVPE802 Figure_6_14_Test_Point_1.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
34.3 3.4 2.26 448 659 417.28
Figure 14. Test Point 1
SN75LVPE802 Figure_6_16_Test_Point_3.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
44.9 13.2 2.31 753.1 649 604.02
Figure 16. Test Point 3
SN75LVPE802 Figure_6_18_Test_Point_4_Without_LV.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
113.3 81.9 2.3 322.8 493 217.48
Figure 18. Test Point 4 Without LVPE802
SN75LVPE802 Figure_6_15_Test_Point_2.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
67.5 38.6 2.11 363.4 595 318.48
Figure 15. Test Point 2
SN75LVPE802 Figure_6_17_Test_Point_4_With_LVPE8.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
57.3 21.5 2.62 672.8 632 442.42
Figure 17. Test Point 4 With LVPE802

7.8.4 Jitter and VOD Results: Case 4 at 8 Gbps

Figure 21 Test Point 3 and Figure 22 Test Point 4 were taken without pre-emphasis.

SN75LVPE802 Figure_6_19_Test_Point_1.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
14.4 10.1 0.31 580 108 274
Figure 19. Test Point 1
SN75LVPE802 Figure_6_21_Test_Point_3.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
30.6 23.6 0.51 406 86 292
Figure 21. Test Point 3
SN75LVPE802 Figure_6_20_Test_Point_2.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
78.1 68.9 0.67 310 45 48
Figure 20. Test Point 2
SN75LVPE802 Figure_6_22_Test_Point_4.gif
TJ DJ RJ Eye Eye Eye
(1e-12) ps (σ-σ) ps (rms) ps Amplitude mV Width ps Opening (mV)
34.4 26.8 0.56 262 85 95
Figure 22. Test Point 4